CY7C1371KV33 CY7C1371KVE33 CY7C1373KV33 18-Mbit (512K 36/1M 18) Flow-Through SRAM with NoBL Architecture (With ECC) 18-Mbit (512K 36/1M 18) Flow-through SRAM with NoBL Architecture (With ECC) Features Functional Description No Bus Latency (NoBL ) architecture eliminates dead cycles The CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33 are between write and read cycles 3.3 V, 512K 36/1M 18 synchronous flow through burst SRAM designed specifically to support unlimited true back-to-back Supports up to 133 MHz bus operations with zero wait states read/write operations with no wait state insertion. The Data is transferred on every clock CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33 are equipped with the advanced No Bus Latency (NoBL) logic Pin-compatible and functionally equivalent to ZBT devices required to enable consecutive read/write operations with data Internally self-timed output buffer control to eliminate the need being transferred on every clock cycle. This feature dramatically to use OE improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions. Registered inputs for flow through operation All synchronous inputs pass through input registers controlled by Byte write capability the rising edge of the clock. The clock input is qualified by the clock enable (CEN) signal, which when deasserted suspends 3.3 V/2.5 V I/O power supply (V ) DDQ operation and extends the previous clock cycle. Maximum Fast clock-to-output times access delay from the clock rise is 6.5 ns (133 MHz device). 6.5 ns (for 133 MHz device) Write operations are controlled by the two or four byte write select (BW ) and a write enable (WE) input. All writes are Clock enable (CEN) pin to enable clock and suspend operation X conducted with on-chip synchronous self-timed write circuitry. Synchronous self-timed writes Three synchronous chip enables (CE , CE , CE ) and an 1 2 3 Asynchronous output enable asynchronous output enable (OE) provide for easy bank selection and output tristate control. To avoid bus contention, the Available in JEDEC-standard Pb-free 100-pin TQFP packages output drivers are synchronously tristated during the data portion of a write sequence. Three chip enables for simple depth expansion Automatic power-down feature available using ZZ mode or CE deselect Burst capability linear or interleaved burst order Low standby power On chip Error Correction Code (ECC) to reduce Soft Error Rate (SER) Selection Guide Description 133 MHz 100 MHz Unit Maximum access time 6.5 8.5 ns Maximum operating current 18 129 114 mA 36 149 134 mA Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-97852 Rev. *F Revised February 8, 2018CY7C1371KV33 CY7C1371KVE33 CY7C1373KV33 Logic Block Diagram CY7C1371KV33 ADDRESS A0, A1, A A1 REGISTER A1 D1 Q1 A0 A0 D0 Q0 MODE BURST CE ADV/LD LOGIC CLK C C CEN WRITE ADDRESS REGISTER O U T P D S U A E T T N ADV/LD A S B MEMORY BW A WRITE E WRITE REGISTRY U ARRAY S DQs F DRIVERS T BW B AND DATA COHERENCY DQP A A F E CONTROL LOGIC DQP B BW C M E E DQP C P R R BW D DQP D S S I WE E N G INPUT E REGISTER OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Logic Block Diagram CY7C1371KVE33 ADDRESS A0, A1, A REGISTER A1 A D Q 1 1 1 MODE A0 Q0 A0 D 0 BURST LOGIC /CE C CLK ADV or /LD C /CEN WRITE ADDRESS REGISTER O D U A S T T E P A DQ N S U DQP A S T ECC S DQP ADV or /LD B WRITE MEMORY E DECODER T DQP C B DRIVERS ARRAY /BWA E DQP D U A WRITE REGISTRY E /BWB F M AND DATA COHERENCY R F /BW P C CONTROL LOGIC I E N S R /BW D G S E /WE ECC INPUT E ENCODER REGISTER READ /OE LOGIC /CE1 CE2 /CE1 SLEEP ZZ CONTROL Document Number: 001-97852 Rev. *F Page 2 of 24