CY7C1370DV25
CY7C1372DV25
18-Mbit (512 K 36/1 M 18)
Pipelined SRAM with NoBL Architecture
18-Mbit (512 K 36/1 M 18) Pipelined SRAM with NoBL Architecture
Features Functional Description
The CY7C1370DV25 and CY7C1372DV25 are 2.5 V, 512 K 36
Pin-compatible and functionally equivalent to ZBT
and 1-Mbit 18 synchronous pipelined burst SRAMs with No
Supports 200-MHz bus operations with zero wait states Bus Latency (NoBL logic, respectively. They are designed
to support unlimited true back-to-back read/write operations with
Available speed grades are 200 and 167 MHz
no wait states. The CY7C1370DV25 and CY7C1372DV25 are
Internally self-timed output buffer control to eliminate the need
equipped with the advanced NoBL logic required to enable
to use asynchronous OE
consecutive read/write operations with data being transferred on
every clock cycle. This feature dramatically improves the
Fully registered (inputs and outputs) for pipelined operation
throughput of data in systems that require frequent write/read
Byte write capability
transitions. The CY7C1370DV25 and CY7C1372DV25 are
pin-compatible and functionally equivalent to ZBT devices.
Single 2.5 V core power supply (V )
DD
All synchronous inputs pass through input registers controlled by
2.5 V I/O power supply (V )
DDQ
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
Fast clock-to-output times
input is qualified by the clock enable (CEN) signal, which when
3.0 ns (for 200-MHz device)
deasserted suspends operation and extends the previous clock
Clock enable (CEN) pin to suspend operation cycle.
Write operations are controlled by the byte write selects
Synchronous self-timed writes
(BW BW for CY7C1370DV25 and BW BW for
a d a b
Available in JEDEC-standard Pb-free 100-pin TQFP, and non
CY7C1372DV25) and a write enable (WE) input. All writes are
Pb-free 165-ball FBGA packages
conducted with on-chip synchronous self-timed write circuitry.
IEEE 1149.1 JTAG-compatible boundary scan Three synchronous chip enables (CE , CE , CE ) and an
1 2 3
asynchronous output enable (OE) provide for easy bank
Burst capability linear or interleaved burst order
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
ZZ sleep mode option and stop clock option
during the data portion of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
Description 200 MHz 167 MHz Unit
Maximum access time 3.0 3.4 ns
Maximum operating current 300 275 mA
Maximum CMOS standby current 70 70 mA
Errata: For information on silicon errata, see Errata on page 30. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 38-05558 Rev. *O Revised November 18, 2014CY7C1370DV25
CY7C1372DV25
Logic Block Diagram CY7C1370DV25
ADDRESS
A0, A1, A
REGISTER 0
A1 A1'
D1 Q1
A0
BURST A0'
D0 Q0
MODE LOGIC
ADV/LD
CLK C
C
CEN
WRITE ADDRESS WRITE ADDRESS
REGISTER 1 REGISTER 2
O
O
S
U
D U
T
E
T
A
P
N P
U T
U
T
ADV/LD S
A
T
WRITE REGISTRY E
R
MEMORY
AND DATA COHERENCY B
BWa WRITE E S DQs
ARRAY
CONTROL LOGIC G U
DRIVERS T DQPa
A
BWb
I F
BWc E DQPb
M S
F
BWd T E DQPc
E
P
E R DQPd
R
S
WE R
S
I
S
E N E
G
INPUT INPUT
E E
REGISTER 1 REGISTER 0
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
ZZ
CONTROL
Document Number: 38-05558 Rev. *O Page 2 of 34