THIS SPEC IS OBSOLETE Spec No: 38-05556 Spec Title: CY7C1371D/CY7C1373D, 18-MBIT (512K X 36/1M X 18) FLOW-THROUGH SRAM WITH NOBL(TM) ARCHITECTURE Replaced by: NONECY7C1371D CY7C1373D 18-Mbit (512K 36/1M 18) Flow-Through SRAM with NoBL Architecture 18-Mbit (512K 36/1M 18) Flow-through SRAM with NoBL Architecture Features Functional Description No Bus Latency (NoBL ) architecture eliminates dead cycles The CY7C1371D/CY7C1373D is a 3.3 V, 512K 36/1M 18 between write and read cycles synchronous flow through burst SRAM designed specifically to support unlimited true back-to-back read/write operations with Supports up to 133-MHz bus operations with zero wait states no wait state insertion. The CY7C1371D/CY7C1373D is Data is transferred on every clock equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read/write operations with data Pin-compatible and functionally equivalent to ZBT devices being transferred on every clock cycle. This feature dramatically Internally self-timed output buffer control to eliminate the need improves the throughput of data through the SRAM, especially to use OE in systems that require frequent write-read transitions. All synchronous inputs pass through input registers controlled by Registered inputs for flow through operation the rising edge of the clock. The clock input is qualified by the Byte write capability clock enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum 3.3 V/2.5 V I/O power supply (V ) DDQ access delay from the clock rise is 6.5 ns (133-MHz device). Fast clock-to-output times Write operations are controlled by the two or four byte write 6.5 ns (for 133-MHz device) select (BW ) and a write enable (WE) input. All writes are X conducted with on-chip synchronous self-timed write circuitry. Clock enable (CEN) pin to enable clock and suspend operation Three synchronous chip enables (CE , CE , CE ) and an 1 2 3 Synchronous self-timed writes asynchronous output enable (OE) provide for easy bank Asynchronous output enable selection and output tristate control. To avoid bus contention, the output drivers are synchronously tristated during the data portion Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free of a write sequence. and non Pb-free 119-ball BGA, and 165-ball FBGA packages For a complete list of related documentation, click here. Three chip enables for simple depth expansion Automatic power-down feature available using ZZ mode or CE deselect IEEE 1149.1 JTAG-compatible boundary scan Burst capability linear or interleaved burst order Low standby power Selection Guide Description 133 MHz 100 MHz Unit Maximum access time 6.5 8.5 ns Maximum operating current 210 175 mA Maximum CMOS standby current 70 70 mA Errata: For information on silicon errata, see Errata on page 36. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05556 Rev. *S Revised November 3, 2016