CY7C1380D CY7C1380F CY7C1382D 18-Mbit (512K 36/1M 18) Pipelined SRAM 18-Mbit (512K 36/1M 18) Pipelined SRAM Features Functional Description Supports bus operation up to 250 MHz The CY7C1380D/CY7C1380F/CY7C1382D SRAM integrates 524,288 36 and 1,048,576 18 SRAM cells with advanced Available speed grades are 250, 200, and 167 MHz synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by Registered inputs and outputs for pipelined operation registers controlled by a positive edge triggered clock input 3.3 V core power supply (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE ), depth-expansion 2.5 V or 3.3 V I/O power supply 1 chip enables (CE and CE ), burst control inputs (ADSC, ADSP, 2 3 Fast clock-to-output times and ADV), write enables (BW , and BWE), and global write X 2.6 ns (for 250 MHz device) (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. Provides high performance 3-1-1-1 access rate Addresses and chip enables are registered at rising edge of User selectable burst counter supporting Intel Pentium clock when address strobe processor (ADSP) or address strobe interleaved or linear burst sequences controller (ADSC) are active. Subsequent burst addresses can Separate processor and controller address strobes be internally generated as they are controlled by the advance pin (ADV). Synchronous self-timed write Address, data inputs, and write controls are registered on-chip Asynchronous output enable to initiate a self-timed write cycle. This part supports byte write Single cycle chip deselect operations (see Pin Definitions on page 6 and Truth Table on page 10 for further details). Write cycles can be one to two or four CY7C1380D/CY7C1382D is available in JEDEC-standard bytes wide as controlled by the byte write control inputs. GW Pb-free 100-pin TQFP package CY7C1380F is available in when active LOW causes all bytes to be written. non Pb-free 165-ball FBGA package The CY7C1380D/CY7C1380F/CY7C1382D operates from a IEEE 1149.1 JTAG-Compatible Boundary Scan +3.3 V core power supply while all outputs operate with a +2.5 ZZ sleep mode option or +3.3 V power supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible. For a complete list of related documentation, click here. Selection Guide Description 250 MHz 200 MHz 167 MHz Unit Maximum Access Time 2.6 3.0 3.4 ns Maximum Operating Current 350 300 275 mA Maximum CMOS Standby Current 70 70 70 mA Errata: For information on silicon errata, see Errata on page 32. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05543 Rev. *S Revised March 29, 2016 Not Recommended for New Designs.CY7C1380D CY7C1380F CY7C1382D Logic Block Diagram CY7C1380D/CY7C1380F A0, A1, A ADDRESS REGISTER 2 A 1:0 MODE ADV Q1 BURST CLK COUNTER AND CLR Q0 LOGIC ADSC ADSP DQ D , DQP D DQ D ,DQP D BYTE BYTE BW D WRITE REGISTER WRITE DRIVER DQ C , DQP C DQ C , DQP C BYTE BW C BYTE OUTPUT WRITE DRIVER OUTPUT WRITE REGISTER MEMORY DQs SENSE BUFFERS ARRAY REGISTERS AMPS DQP A DQ B , DQP B E DQ B , DQP B DQP B BYTE BYTE BW B DQP C WRITE DRIVER WRITE REGISTER DQP D DQ A , DQP A DQ A , DQP A BYTE BYTE BW A WRITE DRIVER WRITE REGISTER BWE INPUT GW REGISTERS ENABLE PIPELINED CE 1 REGISTER ENABLE CE 2 CE 3 OE SLEEP ZZ CONTROL Logic Block Diagram CY7C1382D ADDRESS A0, A1, A REGISTER 2 ADV Q1 BURST CLK COUNTER AND LOGIC ADSC DQ B, DQP B DQ B, DQP B WRITE DRIVER WRITE REGISTER OUTPUT BW B DQs OUTPUT SENSE MEMORY BUFFERS DQP A ARRAY DQP B DQ A,DQP A DQ A,DQP A WRITE DRIVER BW A WRITE REGISTER BWE INPUT GW ENABLE CE 1 PIPELINED REGISTER CE2 ENABLE CE3 OE SLEEP ZZ CONTROL Document Number: 38-05543 Rev. *S Page 2 of 38 Not Recommended for New Designs.