CY7C1381D
CY7C1383D
CY7C1383F
18-Mbit (512 K 36/1 M 18)
Flow-Through SRAM
618-Mbit (512 K 36/1 M 18) Flow Through SRAM
Features Functional Description
Supports 133 MHz bus operations The CY7C1381D/CY7C1383D/CY7C1383F is a 3.3 V,
512 K 36 and 1 M 18 synchronous flow through SRAMs,
512 K 36 and 1 M 18 common I/O
designed to interface with high speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
3.3 V core power supply (V )
DD
6.5 ns (133 MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automatically
2.5 V or 3.3 V I/O supply (V )
DDQ
for the rest of the burst access. All synchronous inputs are gated
Fast clock-to-output time
by registers controlled by a positive edge triggered clock input
(CLK). The synchronous inputs include all addresses, all data
6.5 ns (133 MHz version)
inputs, address pipelining chip enable (CE ), depth-expansion
1
Provides high performance 2-1-1-1 access rate
chip enables (CE and CE ), burst control inputs (ADSC, ADSP,
2 3
and ADV), write enables (BW , and BWE), and global write
x
User selectable burst counter supporting Intel Pentium
(GW). Asynchronous inputs include the output enable (OE) and
interleaved or linear burst sequences
the ZZ pin.
Separate processor and controller address strobes
The CY7C1381D/CY7C1383D/CY7C1383F allows interleaved
or linear burst sequences, selected by the MODE input pin. A
Synchronous self-timed write
HIGH selects an interleaved burst sequence, while a LOW
Asynchronous output enable selects a linear burst sequence. Burst accesses can be initiated
with the processor address strobe (ADSP) or the cache
CY7C1381D available in JEDEC-standard Pb-free 100-pin
controller address strobe (ADSC) inputs. Address advancement
TQFP, Pb-free and non Pb-free 165-ball FBGA package.
is controlled by the address advancement (ADV) input.
CY7C1383D available in JEDEC-standard Pb-free 100-pin
Addresses and chip enables are registered at rising edge of
TQFP. CY7C1383F available in non Pb-free 165-ball FBGA
clock when address strobe processor (ADSP) or address strobe
package.
controller (ADSC) are active. Subsequent burst addresses can
be internally generated as controlled by the advance pin (ADV).
IEEE 1149.1 JTAG-Compatible Boundary Scan
CY7C1381D/CY7C1383D/CY7C1383F operates from a +3.3 V
ZZ sleep mode option
core power supply while all outputs operate with a +2.5 V or +3.3
V supply. All inputs and outputs are JEDEC-standard and
JESD8-5-compatible.
For a complete list of related documentation, click here.
Selection Guide
Description 133 MHz 100 MHz Unit
Maximum Access Time 6.5 8.5 ns
Maximum Operating Current 210 175 mA
Maximum CMOS Standby Current 70 70 mA
Errata: For information on silicon errata, see Errata on page 32. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 38-05544 Rev. *S Revised November 20, 2014CY7C1381D
CY7C1383D
CY7C1383F
Logic Block Diagram CY7C1381D
[1]
(512 K 36)
ADDRESS
A0, A1, A
REGISTER
A[1:0]
MODE
ADV Q1
BURST
CLK
COUNTER
AND LOGIC
Q0
CLR
ADSC
ADSP
DQ D, DQP D
DQ D, DQP D
BYTE
BW D
BYTEBYTE
WRITE REGISTER
WRITE REGISTERWRITE REGISTER
DQ C , DQP C
DQ C , DQP C
BW C
WRITE REGISTER
WRITE REGISTER OUTPUT DQs
MEMORY
SENSE
BUFFERS
ARRAY DQP A
DQ B, DQP B AMPS
DQ B, DQP B DQP B
BW B
DQP C
WRITE REGISTER
WRITE REGISTER DQP D
DQ A, DQP
DQ A, DQP A BYTE
BW A
BYTE WRITE REGISTER
BWE
WRITE REGISTER
INPUT
GW
REGISTERS
ENABLE
CE1
REGISTER
CE2
CE3
OE
SLEEP
Logic Block Diagram CY7C1383D/CY7C1383F
[1]
(1 M 18)
ADDRESS
A0,A1,A
REGISTER
A[1:0]
MODE
ADV Q1
BURST
COUNTER AND
Q0
DQ B,DQP B
DQ B,DQP B
WRITE DRIVER
BW B
MEMORY OUTPUT
DQs
SENSE
ARRAY
BUFFERS
AMPS DQP A
DQ A,DQP A DQP B
DQ A,DQP A
WRITE DRIVER
BW A
BWE
INPUT
GW
REGISTERS
ENABLE
CE 1
CE 2
CE 3
OE
SLEEP
CONTROL
Note
1. CY7C1383F have only 1 chip enable (CE ).
1
Document Number: 38-05544 Rev. *S Page 2 of 37