CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 18-Mbit (512K 36/1M 18) Flow-Through SRAM (With ECC) 18-Mbit (512K 36/1M 18) Flow-Through SRAM (With ECC) Features Functional Description Supports 133 MHz bus operations The CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/ CY7C1383KVE33 are a 3.3 V, 512K 36 and 1M 18 512K 36 and 1M 18 common I/O synchronous flow through SRAMs, designed to interface with high speed microprocessors with minimum glue logic. Maximum 3.3 V core power supply (V ) DD access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and 2.5 V or 3.3 V I/O supply (V ) DDQ increments the address automatically for the rest of the burst Fast clock-to-output time access. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous 6.5 ns (133 MHz version) inputs include all addresses, all data inputs, address pipelining Provides high performance 2-1-1-1 access rate chip enable (CE ), depth-expansion chip enables (CE and 1 2 CE ), burst control inputs (ADSC, ADSP, and ADV), write 3 User selectable burst counter supporting interleaved or linear enables (BW , and BWE), and global write (GW). Asynchronous x burst sequences inputs include the output enable (OE) and the ZZ pin. Separate processor and controller address strobes CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/ The CY7C1383KVE33 allows interleaved or linear burst sequences, Synchronous self-timed write selected by the MODE input pin. A HIGH selects an interleaved Asynchronous output enable burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the processor address CY7C1381KV33/CY7C1381KVE33 available in strobe (ADSP) or the cache controller address strobe (ADSC) JEDEC-standard Pb-free 100-pin TQFP, Pb-free 165-ball inputs. Address advancement is controlled by the address FBGA package. CY7C1383KV33/CY7C1383KVE33 available advancement (ADV) input. in JEDEC-standard Pb-free 100-pin TQFP. Addresses and chip enables are registered at rising edge of clock when address strobe processor (ADSP) or address strobe IEEE 1149.1 JTAG-Compatible Boundary Scan controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the advance pin (ADV). ZZ sleep mode option. CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/ On-chip error correction code (ECC) to reduce soft error rate CY7C1383KVE33 operates from a +3.3 V core power supply (SER) while all outputs operate with a +2.5 V or +3.3 V supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible. Selection Guide Description 133 MHz 100 MHz Unit Maximum access time 6.5 8.5 ns Maximum operating current 18 129 114 mA 36 149 134 mA Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-97888 Rev. *F Revised February 16, 2018CY7C1381KV33/CY7C1381KVE33 CY7C1383KV33/CY7C1383KVE33 Logic Block Diagram CY7C1381KV33 (512K 36) ADDRESS A0, A1, A REGISTER A 1:0 MODE ADV Q1 BURST CLK COUNTER AND LOGIC Q0 CLR ADSC ADSP DQ D, DQP D DQ D, DQP D BYTE BW D BYTEBYTE WRITE REGISTER WRITE REGISTERWRITE REGISTER DQ C , DQP C DQ C , DQP C BW C WRITE REGISTER WRITE REGISTER OUTPUT DQs MEMORY SENSE BUFFERS ARRAY DQP A DQ B, DQP B AMPS DQ B, DQP B DQP B BW B DQP C WRITE REGISTER WRITE REGISTER DQP D DQ A, DQP DQ A, DQP A BYTE BW A BYTE WRITE REGISTER BWE WRITE REGISTER INPUT GW REGISTERS ENABLE CE1 REGISTER CE2 CE3 OE SLEEP Logic Block Diagram CY7C1381KVE33 (512K 36) ADDRESS A0, A1, A REGISTER A 1:0 MODE ADV Q1 BURST CLK COUNTER AND LOGIC Q0 CLR ADSC ADSP DQD, DQPD DQD, DQPD BYTE BWD BYBYTTEE WRITE REGISTER WRITE REGISTERWRITE REGISTER DQC, DQPC DQC, DQPC BYTE BWC BYTE WRITE REGISTER ECC WRITE REGISTER OUTPUT DQs MEMORY SENSE DECODER BUFFERS ARRAY DQPA DQB, DQPB AMPS DQB, DQPB DQPB BYTE BWB BYTE DQPC WRITE REGISTER WRITE REGISTER DQPD DQA, DQPA DQA, DQPA BYTE BWA BYTE WRITE REGISTER BWE WRITE REGISTER ECC INPUT GW ENCODER REGISTERS ENABLE CE1 REGISTER CE2 CE3 OE SLEEP ZZ CONTROL Document Number: 001-97888 Rev. *F Page 2 of 34