CY7C1386KV33 CY7C1387KV33 18-Mbit (512K 36/1M 18) Pipelined DCD Sync SRAM 18-Mbit (512K 36/1M 18) Pipelined DCD Sync SRAM Features Functional Description Supports bus operation up to 200 MHz The CY7C1386KV33/CY7C1387KV33 SRAM integrates 512K 36/1M 18 SRAM cells with advanced synchronous Available speed grades are 200, and 167 MHz peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers Registered inputs and outputs for pipelined operation controlled by a positive edge triggered clock input (CLK). The Optimal for performance (double-cycle deselect) synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE ), depth expansion chip Depth expansion without wait state 1 enables (CE and CE ), burst control inputs (ADSC, ADSP, and 2 3 3.3 V core power supply (V ) DD ADV), write enables ( , and BWE), and global write (GW). BW X Asynchronous inputs include the output enable (OE) and the ZZ 2.5 V or 3.3 V I/O power supply (V DDQ) pin. Fast clock-to-output times Addresses and chip enables are registered at rising edge of 3 ns (for 200 MHz device) clock when either address strobe processor (ADSP) or address Provides high performance 3-1-1-1 access rate strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the User selectable burst counter supporting interleaved or linear advance pin (ADV). burst sequences Address, data inputs, and write controls are registered on-chip Separate processor and controller address strobes to initiate a self timed write cycle.This part supports byte write operations (see Pin Configurations on page 5 and Truth Table on Synchronous self-timed writes page 9 for further details). Write cycles can be one to four bytes Asynchronous output enable wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an CY7C1386KV33 available in JEDEC-standard Pb-free 100-pin additional pipelined enable register which delays turning off the TQFP. CY7C1387KV33 available in JEDEC-standard Pb-free output buffers an additional cycle when a deselect is 100-pin TQFP executed.This feature allows depth expansion without penalizing ZZ sleep mode option system performance. The CY7C1386KV33/CY7C1387KV33 operates from a +3.3 V core power supply while all outputs operate with a +3.3 V or +2.5 V supply. All inputs and outputs are JEDEC-standard and JESD8-5-compatible. Selection Guide Description 200 MHz 167 MHz Unit Maximum access time 3.0 3.4 ns Maximum operating current 18 158 143 mA 36 178 163 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-97893 Rev. *E Revised February 8, 2018CY7C1386KV33 CY7C1387KV33 Logic Block Diagram CY7C1386KV33 ADDRESS A0,A1,A REGISTER 2 A 1:0 MODE Q1 ADV BURST CLK COUNTER AND LOGIC CLR Q0 ADSC ADSP DQ D,DQP D DQ D,DQP D BYTE BYTE BW D WRITE REGISTER WRITE DRIVER DQ c,DQP C DQ c,DQP C MEMORY BYTE BW C BYTE ARRAY OUTPUT WRITE DRIVER OUTPUT WRITE REGISTER SENSE DQs BUFFERS REGISTERS AMPS DQP A DQ B,DQP B E DQ B,DQP B DQP B BYTE BYTE BW B DQP C WRITE DRIVER WRITE REGISTER DQP D DQ A,DQP A DQ A,DQP A BYTE BYTE BW A WRITE DRIVER WRITE REGISTER BWE INPUT GW REGISTERS ENABLE PIPELINED CE 1 REGISTER ENABLE CE 2 CE 3 OE ZZ CONTROL Document Number: 001-97893 Rev. *E Page 2 of 23