CY7C1416BV18, CY7C1427BV18 CY7C1418BV18, CY7C1420BV18 36-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) The CY7C1416BV18, CY7C1427BV18, CY7C1418BV18, and CY7C1420BV18 are 1.8V Synchronous Pipelined SRAM 267 MHz clock for high bandwidth equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and 2-word burst for reducing address bus frequency a 1-bit burst counter. Addresses for read and write are latched Double Data Rate (DDR) interfaces on alternate rising edges of the input (K) clock. Write data is (data transferred at 534 MHz) at 267 MHz for DDR-II registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising Two input clocks (K and K) for precise DDR timing edge of K and K if C/C are not provided. Each address location SRAM uses rising edges only is associated with two 8-bit words in the case of CY7C1416BV18 Two input clocks for output data (C and C) to minimize clock and two 9-bit words in the case of CY7C1427BV18 that burst sequentially into or out of the device. The burst counter always skew and flight time mismatches starts with a 0 internally in the case of CY7C1416BV18 and Echo clocks (CQ and CQ) simplify data capture in high-speed CY7C1427BV18. On CY7C1418BV18 and CY7C1420BV18, the systems burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of Synchronous internally self-timed writes CY7C1418BV18 and two 36-bit words in the case of DDR-II operates with 1.5 cycle read latency when DLL is CY7C1420BV18 sequentially into or out of the device. enabled Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same Operates as a DDR-I device with 1 cycle read latency in DLL physical pins as the data inputs D) are tightly matched to the two off mode output echo clocks CQ/CQ, eliminating the need for separately 1.8V core power supply with HSTL inputs and outputs capturing data from each individual DDR SRAM in the system design. Output data clocks (C/C) enable maximum system Variable drive HSTL output buffers clocking and data synchronization flexibility. Expanded HSTL output voltage (1.4VV ) DD All synchronous inputs pass through input registers controlled by Available in 165-Ball FBGA package (15 x 17 x 1.4 mm) the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock Offered in both in Pb-free and non Pb-free packages domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. JTAG 1149.1 compatible test access port Delay Lock Loop (DLL) for accurate data placement Configurations CY7C1416BV18 4M x 8 CY7C1427BV18 4M x 9 CY7C1418BV18 2M x 18 CY7C1420BV18 1M x 36 Selection Guide Description 267 MHz 250 MHz 200 MHz 167 MHz Unit Maximum Operating Frequency 267 250 200 167 MHz Maximum Operating Current x8 795 725 600 500 mA x9 800 725 600 500 x18 835 760 620 525 x36 910 825 675 570 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-07033 Rev. *D Revised June 17, 2008 + Feedback 2M x 8 Array 2M x 9 Array 2M x 8 Array 2M x 9 Array CY7C1416BV18, CY7C1427BV18 CY7C1418BV18, CY7C1420BV18 Logic Block Diagram (CY7C1416BV18) Write Write 21 A Reg Reg (20:0) Address Register 8 LD K Output CLK R/W K Logic Gen. Control C DOFF Read Data Reg. C 16 CQ V 8 REF 8 Reg. Reg. Control CQ R/W Logic 8 8 NWS 1:0 Reg. 8 DQ 7:0 Logic Block Diagram (CY7C1427BV18) Write Write 21 A Reg Reg (20:0) Address Register 9 LD K Output CLK R/W K Logic Gen. Control C DOFF Read Data Reg. C 18 CQ V 9 REF 9 Reg. Reg. Control CQ R/W Logic 9 9 BWS 0 Reg. 9 DQ 8:0 Document Number: 001-07033 Rev. *D Page 2 of 29 + Feedback Write Add. Decode Write Add. Decode Read Add. Decode Read Add. Decode