CY7C1423KV18/CY7C1424KV18 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features Configurations 36-Mbit density (2M 18, 1M 36) CY7C1423KV18 2M 18 CY7C1424KV18 1M 36 333 MHz clock for high bandwidth Two-word burst for reducing address bus frequency Functional Description Double data rate (DDR) interfaces (data transferred at The CY7C1423KV18, and CY7C1424KV18 are 1.8 V 666 MHz) at 333 MHz synchronous pipelined SRAMs, equipped with DDR II SIO (double data rate separate I/O) architecture. The DDR II SIO Two input clocks (K and K) for precise DDR timing consists of two separate ports: the read port and the write port to SRAM uses rising edges only access the memory array. The read port has data outputs to Two input clocks for output data (C and C) to minimize clock support read operations and the write port has data inputs to skew and flight time mismatches support write operations. The DDR II SIO has separate data inputs and data outputs to completely eliminate the need to Echo clocks (CQ and CQ) simplify data capture in high speed turnaround the data bus required with common I/O devices. systems Access to each port is accomplished through a common address Synchronous internally self timed writes bus. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising DDR II operates with 1.5 cycle read latency when DOFF is edges of both K and K. Read data is driven on the rising edges asserted HIGH of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 18-bit Operates similar to DDR I device with 1 cycle read latency when words in the case of CY7C1423KV18, and two 36-bit words in DOFF is asserted LOW the case of CY7C1424KV18 that burst sequentially into or out of 1.8 V core power supply with HSTL inputs and outputs the device. Variable drive HSTL output buffers Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs are tightly matched to the Expanded HSTL output voltage (1.4 V to V ) DD two output echo clocks CQ/CQ, eliminating the need to capture Supports both 1.5 V and 1.8 V IO supply data separately from each individual DDR II SIO SRAM in the system design. Output data clocks (C/C) enable maximum Available in 165-ball FBGA package (13 15 1.4 mm) system clocking and data synchronization flexibility. Offered in both Pb-free and non Pb-free packages All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output JTAG 1149.1 compatible test access port registers controlled by the C or C (or K or K in a single clock Phase locked loop (PLL) for accurate data placement domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. For a complete list of related documentation, click here. Selection Guide Description 333 MHz 300 MHz 250 MHz Unit Maximum operating frequency 333 300 250 MHz Maximum operating current 18 490 460 430 mA 36 600 Not Offered 490 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-57829 Rev. *J Revised January 4, 20181M x 18 Array 512K x 18 Array 1M x 18 Array 512K x 18 Array CY7C1423KV18/CY7C1424KV18 Logic Block Diagram CY7C1423KV18 18 D 17:0 Write Write Data Reg Data Reg 20 Address A (19:0) Register LD K Control R/W CLK Logic K Gen. C DOFF Read Data Reg. C CQ 36 R/W 18 CQ Reg. Reg. V 18 REF Control Logic 18 LD Reg. 18 Q 18 17:0 BWS 1:0 Logic Block Diagram CY7C1424KV18 36 D 35:0 Write Write Data Reg Data Reg 19 Address A (18:0) Register LD K Control R/W CLK Logic K Gen. C DOFF Read Data Reg. C CQ 72 R/W 36 CQ Reg. Reg. V 36 REF Control Logic 36 LD Reg. 36 Q 36 35:0 BWS 3:0 Document Number: 001-57829 Rev. *J Page 2 of 31 Write Add. Decode Write Add. Decode Read Add. Decode Read Add. Decode