CY7C1440AV33 36-Mbit (1 M 36) Pipelined Sync SRAM 36-Mbit (1 M 36) Pipelined Sync SRAM Features Functional Description Supports bus operation up to 250 MHz The CY7C1440AV33 SRAM integrates 1 M 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter Available speed grades are 250 and 167 MHz for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input Registered inputs and outputs for pipelined operation (CLK). The synchronous inputs include all addresses, all data 3.3 V core power supply inputs, address-pipelining chip enable (CE ), depth-expansion 1 chip enables (CE and CE ), burst control inputs (ADSC, ADSP, 2 3 2.5 V/3.3 V I/O power supply and ADV), write enables (BW and BWE), and global write (GW). X Fast clock-to-output times Asynchronous inputs include the output enable (OE) and the ZZ pin. 2.6 ns (for 250-MHz device) Addresses and chip enables are registered at rising edge of Provide high-performance 3-1-1-1 access rate clock when either address strobe processor (ADSP) or address User-selectable burst counter supporting Intel Pentium strobe controller (ADSC) are active. Subsequent burst interleaved or linear burst sequences addresses can be internally generated as controlled by the advance pin (ADV). Separate processor and controller address strobes Address, data inputs, and write controls are registered on-chip Synchronous self-timed writes to initiate a self-timed write cycle.This part supports byte write operations (see pin descriptions and truth table for further Asynchronous output enable details). Write cycles can be one to two or four bytes wide as Single cycle chip deselect controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. CY7C1440AV33 available in Pb-free 100-pin TQFP package, The CY7C1440AV33 operates from a +3.3 V core power supply Pb-free 165-ball FBGA package. while all outputs may operate with either a +2.5 or +3.3 V supply. IEEE 1149.1 JTAG-compatible boundary scan All inputs and outputs are JEDEC-standard JESD8-5-compatible. ZZ sleep mode option For a complete list of related documentation, click here. Selection Guide Description 250 MHz 167 MHz Unit Maximum access time 2.6 3.4 ns Maximum operating current 475 375 mA Maximum CMOS standby current 120 120 mA Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05383 Rev. *M Revised December 16, 2014CY7C1440AV33 Logic Block Diagram CY7C1440AV33 A0, A1, A ADDRESS REGISTER 2 A 1:0 MODE ADV Q1 CLK BURST COUNTER AND CLR Q0 LOGIC ADSC ADSP DQD ,DQPD DQD ,DQPD BYTE BYTE BWD WRITE REGISTER WRITE DRIVER DQC ,DQPC DQC ,DQPC BYTE BYTE BWC OUTPUT WRITE DRIVER WRITE REGISTER OUTPUT MEMORY SENSE DQs BUFFERS ARRAY REGISTERS AMPS DQPA DQB ,DQPB E DQB ,DQPB DQPB BYTE BYTE BWB DQPC WRITE DRIVER WRITE REGISTER DQPD DQA ,DQPA DQA ,DQPA BYTE BWA BYTE WRITE DRIVER WRITE REGISTER BWE INPUT GW REGISTERS ENABLE PIPELINED CE1 REGISTER ENABLE CE2 CE3 OE SLEEP ZZ CONTROL Document Number: 38-05383 Rev. *M Page 2 of 33