CY7C1441AV33 36-Mbit (1 M 36) Flow-Through SRAM 36-Mbit (1 M 36) Flow-Through SRAM Features Functional Description Supports 133-MHz bus operations The CY7C1441AV33 are 3.3 V, 1 M 36 Synchronous Flow-through SRAMs, respectively designed to interface with 1 M 36 common I/O high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit 3.3 V core power supply on-chip counter captures the first address in a burst and 2.5 V or 3.3 V I/O power supply increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled Fast clock-to-output times by a positive-edge-triggered Clock Input (CLK). The 6.5 ns (133-MHz version) synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE ), depth-expansion Chip Provide high-performance 2-1-1-1 access rate 1 Enables (CE and CE ), Burst Control inputs (ADSC, ADSP, and 2 3 User-selectable burst counter supporting Intel Pentium ADV), Write Enables (BW , and BWE), and Global Write (GW). x interleaved or linear burst sequences Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Separate processor and controller address strobes The CY7C1441AV33 allows either interleaved or linear burst Synchronous self-timed write sequences, selected by the MODE input pin. A HIGH selects an Asynchronous output enable interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor CY7C1441AV33 available in JEDEC-standard Pb-free 100-pin Address Strobe (ADSP) or the cache Controller Address Strobe TQFP package, Pb-free 165-ball FBGA package. (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. IEEE 1149.1 JTAG-Compatible Boundary Scan Addresses and chip enables are registered at rising edge of ZZ Sleep Mode option clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1441AV33 operates from a +3.3 V core power supply while all outputs may operate with either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. For a complete list of related documentation, click here. Selection Guide Description 133 MHz Unit Maximum Access Time 6.5 ns Maximum Operating Current 310 mA Maximum CMOS Standby Current 120 mA Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05357 Rev. *M Revised December 29, 2014CY7C1441AV33 Logic Block Diagram CY7C1441AV33 ADDRESS A0, A1, A REGISTER A 1:0 MODE ADV Q1 BURST CLK COUNTER AND LOGIC Q0 CLR ADSC ADSP DQ D, DQP D DQ D, DQP D BYTE BW D BYTEBYTE WRITE REGISTER WRITE REGISTERWRITE REGISTER DQ C, DQP C DQ C, DQP C BYTE BW C BYTE WRITE REGISTER WRITE REGISTER OUTPUT DQ s MEMORY SENSE BUFFERS ARRAY DQP A DQ B, DQP B AMPS DQ B, DQP B DQP B BYTE BW B BYTE DQP C WRITE REGISTER DQP D WRITE REGISTER DQ A, DQP A DQ A, DQPA BYTE BW A BYTE WRITE REGISTER BWE WRITE REGISTER INPUT GW REGISTERS ENABLE CE1 REGISTER CE2 CE3 OE SLEEP ZZ CONTROL Document Number: 38-05357 Rev. *M Page 2 of 34