CY7C1440KV33 CY7C1442KV33 CY7C1440KVE33 36-Mbit (1M 36/2M 18) Pipelined Sync SRAM (With ECC) 36-Mbit (1M 36/2M 18) Pipelined Sync SRAM (With ECC) Features Functional Description Supports bus operation up to 250 MHz The CY7C1440KV33/CY7C1442KV33/CY7C1440KVE33 SRAM integrate 1M 36/2M 18/1M 36 SRAM cells with advanced Available speed grades are 250 MHz and 167 MHz synchronous peripheral circuitry and a two-bit counter for Registered inputs and outputs for pipelined operation internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input 3.3 V core power supply (CLK). The synchronous inputs include all addresses, all data 2.5 V or 3.3 V I/O power supply inputs, address-pipelining chip enable (CE ), depth-expansion 1 chip enables (CE and CE ), burst control inputs (ADSC, ADSP, 2 3 Fast clock-to-output time and ADV), write enables (BW and BWE), and global write (GW). X 2.5 ns (for 250 MHz device) Asynchronous inputs include the output enable (OE) and the ZZ Provide high-performance 3-1-1-1 access rate pin. User-selectable burst counter supporting interleaved or linear Addresses and chip enables are registered at rising edge of burst sequences clock when either address strobe processor (ADSP) or address strobe controller (ADSC) are active. Subsequent burst Separate processor and controller address strobes addresses can be internally generated as controlled by the Synchronous self-timed writes advance pin (ADV). Asynchronous output enable Address, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle. This part supports byte write Single cycle chip deselect operations (see pin descriptions and truth table for further CY7C1440KV33, CY7C1442KV33 and CY7C1440KVE33 are details). Write cycles can be one, two or four bytes wide as available in Pb-free 100-pin TQFP, and Pb-free and non Pb-free controlled by the byte write control inputs. GW when active LOW 165-ball FBGA packages. causes all bytes to be written. IEEE 1149.1 JTAG-compatible boundary scan The CY7C1440KV33/CY7C1442KV33/CY7C1440KVE33 ZZ sleep mode option operate from a +3.3 V core power supply while all outputs may operate with either a +2.5 V or +3.3 V supply. All inputs and On-Chip error correction code (ECC) to reduce soft error rate outputs are JEDEC-standard JESD8-5-compatible. (SER) Selection Guide Description 250 MHz 167 MHz Unit Maximum access time 2.5 3.4 ns Maximum operating current 18 220 Not Offered mA 36 240 190 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-66676 Rev. *G Revised July 5, 2016CY7C1440KV33 CY7C1442KV33 CY7C1440KVE33 Logic Block Diagram CY7C1440KV33 A0, A1, A ADDRESS REGISTER 2 A 1:0 MODE ADV Q1 CLK BURST COUNTER AND CLR Q0 LOGIC ADSC ADSP DQD ,DQPD DQD ,DQPD BYTE BYTE BWD WRITE REGISTER WRITE DRIVER DQC ,DQPC DQC ,DQPC BYTE BYTE BWC OUTPUT WRITE DRIVER WRITE REGISTER OUTPUT MEMORY SENSE DQs BUFFERS ARRAY REGISTERS AMPS DQPA DQB ,DQPB E DQB ,DQPB DQPB BYTE BYTE BWB DQPC WRITE DRIVER WRITE REGISTER DQPD DQA ,DQPA DQA ,DQPA BYTE BWA BYTE WRITE DRIVER WRITE REGISTER BWE INPUT GW REGISTERS ENABLE PIPELINED CE1 REGISTER ENABLE CE2 CE3 OE SLEEP ZZ CONTROL Logic Block Diagram CY7C1442KV33 ADDRESS A0, A1, A REGISTER A 1:0 2 MODE ADV Q1 BURST CLK COUNTER AND LOGIC CLR Q0 ADSC ADSP DQB,DQPB DQB,DQPB WRITE DRIVER WRITE REGISTER BWB OUTPUT DQs SENSE OUTPUT MEMORY BUFFERS DQPA AMPS ARRAY REGISTERS DQPB DQA,DQPA E DQA,DQPA WRITE DRIVER BWA WRITE REGISTER BWE INPUT GW REGISTERS ENABLE CE1 PIPELINED REGISTER CE2 ENABLE CE3 OE SLEEP ZZ CONTROL Document Number: 001-66676 Rev. *G Page 2 of 33