THIS SPEC IS OBSOLETE Spec No: 38-05352 Spec Title: CY7C1444AV33, 36-MBIT (1M X 36) PIPELINED DCD SYNC SRAM Replaced by: NoneCY7C1444AV33 36-Mbit (1M 36) Pipelined DCD Sync SRAM 36-Mbit (1M 36) Pipelined DCD Sync SRAM Features Functional Description Supports bus operation up to 250 MHz The CY7C1444AV33 SRAM integrates 1M 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter Available speed grades are 250 MHz and 167 MHz for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input Registered inputs and outputs for pipelined operation (CLK). The synchronous inputs include all addresses, all data Optimal for performance (double-cycle deselect) inputs, address-pipelining chip enable (CE ), depth-expansion 1 chip enables (CE and CE ), burst control inputs (ADSC, ADSP, 2 3 Depth expansion without wait state and ADV), write enables (BW , and BWE), and global write X 3.3 V core power supply (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. 2.5 V/3.3 V I/O power supply Addresses and chip enables are registered at rising edge of Fast clock-to-output times clock when either address strobe processor (ADSP) or address 2.6 ns (for 250-MHz device) strobe controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Provide high-performance 3-1-1-1 access rate advance pin (ADV). User-selectable burst counter supporting Intel Pentium Address, data inputs, and write controls are registered on-chip interleaved or linear burst sequences to initiate a self-timed write cycle. This part supports byte write operations (see Pin Descriptions and Truth Table for further Separate processor and controller address strobes details). Write cycles can be one to four bytes wide as controlled Synchronous self-timed writes by the byte write control inputs. GW active LOW causes all bytes This device incorporates an additional pipelined to be written. Asynchronous output enable enable register which delays turning off the output buffers an additional cycle when a deselect is executed. This feature allows CY7C1444AV33 available in JEDEC-standard Pb-free 100-pin depth expansion without penalizing system performance. TQFP package The CY7C1444AV33 operates from a +3.3 V core power supply ZZ sleep mode option while all outputs operate with a +3.3 V or a +2.5 V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. For a complete list of related documentation, click here. Selection Guide Description 250 MHz 167 MHz Unit Maximum access time 2.6 3.4 ns Maximum operating current 475 375 mA Maximum CMOS standby current 120 120 mA Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05352 Rev. *N Revised November 2, 2016