CY7C144, CY7C145 8K x 8/9 Dual-Port Static RAM with SEM, INT, BUSY Features Functional Description True Dual-Ported Memory Cells that Enable Simultaneous The CY7C144 and CY7C145 are high speed CMOS 8K x 8 and Reads of the same Memory Location 8K x 9 dual-port static RAMs. Various arbitration schemes are included on the CY7C144/5 to handle situations when multiple 8K x 8 Organization (CY7C144) processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for 8K x 9 Organization (CY7C145) reads and writes to any location in memory. The CY7C144/5 can 0.65-Micron CMOS for optimum Speed and Power be used as a standalone 64/72-Kbit dual-port static RAM or multiple devices can be combined in order to function as a High Speed Access: 15 ns 16/18-bit or wider master/slave dual-port static RAM. An M/S pin Low Operating Power: I = 160 mA (max.) is provided for implementing 16/18-bit or wider memory applica- CC tions without the need for separate master and slave devices or Fully Asynchronous Operation additional discrete logic. Application areas include interpro- cessor/multiprocessor designs, communications status Automatic Power Down buffering, and dual-port video/graphics memory. TTL Compatible Each port has independent control pins: chip enable (CE), read Master/Slave Select Pin enables Bus Width Expansion to 16/18 or write enable (R/W), and output enable (OE). Two flags, BUSY Bits or more and INT, are provided on each port. BUSY signals that the port is trying to access the same location currently being accessed Busy Arbitration Scheme provided by the other port. The interrupt flag (INT) permits communication between ports or systems by means of a mail box. The Semaphores included to permit Software Handshaking semaphores are used to pass a flag, or token, from one port to between Ports the other to indicate that a shared resource is in use. The INT Flag for Port-to-Port Communication semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a Available in 68-pin PLCC, 64-pin and 80-pin TQFP semaphore indicates that a shared resource is in use. An Pb-free Packages available automatic power down feature is controlled independently on each port by a chip enable (CE) pin or SEM pin. R/W L R/W Logic Block Diagram R CE CE L R OE OE R L (7C145) I/O I/O (7C145) 8L 8R I/O 7L I/O 7R I/O I/O CONTROL CONTROL I/O 0L I/O 0R 1, 2 1, 2 BUSY BUSY L R A 12L A 12R MEMORY ADDRESS ADDRESS ARRAY A0L A 0R DECODER DECODER INTERRUPT CEL SEMAPHORE CE R ARBITRATION OE L OE R R/W L R/W R SEM SEM L R INT 2 INT 2 L R M/S Notes 1. BUSY is an output in master mode and an input in slave mode. 2. Interrupt: push-pull output and requires no pull-up resistor. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document : 38-06034 Rev. *F Revised March 22, 2010 + Feedback CY7C144, CY7C145 Pin Configuration Figure 1. 68-Pin PLCC (Top View) Figure 2. 64-Pin TQFP (Top View) 98 7 6 5 432168 67666564636261 IO 2L 10 60 A 5L IO 3L A 11 59 4L IO 48 A 2L 1 4L IO 4L A 12 58 3L IO 2 47 A 3L 3L IO 5L A 13 57 2L A IO 46 2L 4L 3 GND A 14 56 1L IO 4 45 A 5L 1L IO 6L 15 55 A 0L GND 44 A 5 0L IO 7L INT 16 54 L IO 6 43 INT 6L L V CC BUSY 17 53 L CY7C144/5 IO 42 BUSY 7L 7 L GND GND 18 52 V GND 8 CY7C144 41 IO CC 0R 19 51 M/S M/S GND 40 IO 9 1R 20 50 BUSY R 39 BUSY IO 10 IO 0R R 2R 49 21 INT R V IO 38 INT A 1R 11 R CC 48 22 0R IO 37 A IO 2R 12 3R A 0R 23 47 1R A IO V 13 36 1R 4R A CC 24 46 2R A IO IO 35 5R 25 45 3R 14 2R A 3R IO IO 15 34 A 6R 26 44 A 4R 3R 4R 2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43 IO 33 A 5R 16 4R Figure 3. 80-Pin TQFP (Top View) NC 1 60 NC I/O A 2L 2 59 5L I/O A 3 4L 3L 58 I/O A 4 3L 4L 57 I/O A 5 2L 5L 56 A GND 6 1L 55 I/O A 6L 7 0L 54 I/O 7L 8 INT 53 L BUSY V CC 9 L 52 GND 10 CY7C145 NC 51 M/S GND 11 50 I/O 0R BUSY 12 R 49 I/O 1R 13 INT 48 R I/O 2R A 14 0R 47 V CC A 15 1R 46 I/O A 3R 16 45 2R I/O 4R A 17 3R 44 I/O 5R 18 A 43 4R I/O 6R 19 NC 42 NC 20 NC 41 Notes: 3. I/O on the CY7C145. 8R 4. I/O on the CY7C145. 8L Document : 38-06034 Rev. *F Page 2 of 20 + Feedback IO 7R IO 1L 3 NC IO 0L OE R 4 NC R/W OE R L SEM R/W R L CE SEM R L CE NC L NC NC GND NC A V 12R CC A A 11R 12L A A 10R 11L A A 9R 10L I/O I/O 7R 21 80 A 1L A 8R 9L I/O I/O 8R 0L 22 79 A A 7R 8L OE I/O R 23 78 8L A A 6R 7L R/W R 24 77 OE A L A 5R 6L SEM R/W R 25 76 L CE R 26 75 SEM L NC CE 27 74 L NC NC 28 73 NC NC 29 72 NC GND 30 71 A V 12R 31 70 CC A A 11R 32 69 12L A A 10R 33 68 11L A 9R A 34 67 10L A A 8R 9L 35 66 A A 7R 36 65 8L A A 6R 37 64 7L IO 17 IO 6R 64 1L A 5R A 38 63 6L IO 18 IO 7R 63 0L NC 39 62 NC OE 19 OE R 62 L NC 20 NC 40 61 R/W 61 R/W R L 21 SEM 60 SEM R L 22 59 CE CE R L 23 NC 58 NC 24 GND 57 V CC 25 A 56 A 12R 12L 26 55 A A 11R 11L 27 A 54 A 10R 10L 28 53 A A 9R 9L 29 52 A A 8R 8L 30 A 51 A 7R 7L 31 50 A A 6R 6L 32 A 49 A 5R 5L