CY7C144AV-25AXC Infineon

CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3 V 8 K / 16 K 8 Asynchronous Dual-Port Static RAM CY7C144AV CY7C006AV 3.3 V 8 K / 16 K 8 Asynchronous Dual-Port Static RAM 3.3 V 8 K / 16 K 8 Dual-Port Static RAM Expandable data bus to 16 bits or more using Master/ Slave Features chip select when using more than one device True dual-ported memory cells which allow simultaneous On-chip arbitration logic access of the same memory location Semaphores included to permit software handshaking 8 K / 16 K 8 organizations (CY7C144AV/CY7C006AV) between ports 0.35-micron complementary metal oxide semiconductor INT flag for port-to-port communication (CMOS) for optimum speed/power Pin select for Master or Slave High-speed access: 25 ns Available in 64-pin thin quad flat pack (TQFP) (7C006AV and Low operating power 7C144AV) Active: I = 115 mA (typical) CC Pb-free packages available Standby: I = 10 A (typical) SB3 Fully asynchronous operation Functional Description Automatic power-down For a complete list of related documentation, click here. Logic Block Diagram R/W R/W L R CE CE L R OE OE L R 8 8 1 1 I/O I/O I/O I/O 0L 7L 0R 7R I/O I/O Control Control 1314 1314 2 Address Address 2 True Dual-Ported A A A A 0L 1213L 0R 1213R RAM Array Decode Decode 1314 1314 2 2 A A A A 0L 1213L 0R 1213R CE CE Interrupt L R OE OE Semaphore L R R/W Arbitration R/W L R SEM SEM L R 3 3 BUSY BUSY L R INT INT L R M/S Notes 1. I/O I/O for 8 devices. 0 7 2. A A for 8K devices A A for 16K devices. 0 12 0 13 3. BUSY is an output in master mode and an input in slave mode. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-06051 Rev. *J Revised September 14, 2015CY7C144AV CY7C006AV Contents Pin Configurations ...........................................................3 Non-Contending Read/Write .......................................... 16 Selection Guide ................................................................4 Interrupt Operation Example ......................................... 16 Pin Definitions ..................................................................4 Semaphore Operation Example .................................... 16 Architecture ......................................................................4 Ordering Information ...................................................... 17 Functional Overview ........................................................4 8 K 8 3.3 V Asynchronous Dual-Port SRAM .......... 17 Read and Write Operations .........................................4 16 K 8 3.3 V Asynchronous Dual-Port SRAM ........ 17 Interrupts .....................................................................5 Ordering Code Definitions ......................................... 17 Busy ............................................................................5 Package Diagrams .......................................................... 18 Master/Slave ...............................................................5 Acronyms ........................................................................19 Semaphore Operation .................................................5 Document Conventions ................................................. 19 Maximum Ratings .............................................................6 Units of Measure ....................................................... 19 Operating Range ...............................................................6 Document History Page ................................................. 20 Electrical Characteristics .................................................6 Sales, Solutions, and Legal Information ...................... 21 Capacitance ......................................................................6 Worldwide Sales and Design Support ....................... 21 AC Test Loads and Waveforms .......................................7 Products ....................................................................21 Data Retention Mode ........................................................7 PSoC Solutions ...................................................... 21 Timing ................................................................................7 Cypress Developer Community ................................. 21 Switching Characteristics ................................................8 Technical Support ..................................................... 21 Switching Waveforms ....................................................10 Document Number: 38-06051 Rev. *J Page 2 of 21