CY7C144E
8 K 8 Dual-port Static RAM
with SEM, INT, BUSY
Features Functional Description
True dual-ported memory cells that enable simultaneous reads The CY7C144E is a high speed CMOS 8 K 8 dual port static
of the same memory location RAM. Various arbitration schemes are included on the
CY7C144E to handle situations when multiple processors
8 K 8 organization (CY7C144E)
access the same piece of data. Two ports are provided permitting
independent, asynchronous access for reads and writes to any
0.35-micron CMOS for optimum speed and power
location in memory. The CY7C144E can be used as a
High-speed access: 15 ns
standalone 64-Kbit dual-port static RAM or multiple devices can
be combined in order to function as a 16-bit or wider master /
Low operating power: I = 180 mA (typical),
CC
slave dual-port static RAM. An M/S pin is provided for
standby ISB3 = 0.05 mA (typical)
implementing 16-bit or wider memory applications without the
Fully asynchronous operation need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor /
Automatic power-down
multiprocessor designs, communications status buffering, and
dual-port video / graphics memory.
TTL compatible
Each port has independent control pins: chip enable (CE), read
Master / slave select pin enables bus width expansion to 16-bits
or write enable (R/W), and output enable (OE). Two flags, BUSY
or more
and INT, are provided on each port. BUSY signals that the port
Busy arbitration scheme provided is trying to access the same location currently being accessed
by the other port. The interrupt flag (INT) permits communication
Semaphores included to permit software handshaking
between ports or systems by means of a mail box. The
between ports
semaphores are used to pass a flag, or token, from one port to
the other to indicate that a shared resource is in use. The
INT flag for port-to-port communication
semaphore logic is comprised of eight shared latches. Only one
Available in 68-pin PLCC and 64-pin TQFP
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
Pb-free packages available
automatic power-down feature is controlled independently on
each port by a chip enable (CE) pin or SEM pin.
For a complete list of related documentation, click here.
Logic Block Diagram
R/W L
R/W
R
CEL CER
OE
OE R
L
I/O
7L I/O7R
I/O I/O
CONTROL CONTROL
I/O
0L I/O
0R
[1, 2]
BUSY [1, 2]
L BUSY
R
A12L A
12R
MEMORY
ADDRESS ADDRESS
ARRAY
A A
0L DECODER DECODER 0R
INTERRUPT
CE SEMAPHORE
L CE
R
ARBITRATION
OE
L
OE
R
R/W L R/W
R
SEM L SEM
R
[2]
INT INT [2]
L R
M/S
Notes
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document #: 001-63982 Rev. *C Revised November 7, 2014CY7C144E
Contents
Pin Configuration .............................................................3 Switching Characteristics ................................................ 9
Architecture ......................................................................4 Switching Waveforms .................................................... 11
Functional Description .....................................................4 Ordering Code Definitions ......................................... 18
Write Operation ...........................................................4 Package Diagrams .......................................................... 19
Read Operation ...........................................................4 Acronyms ........................................................................21
Interrupts .....................................................................4 Reference Documents .................................................... 21
Busy ............................................................................4 Document Conventions ................................................. 21
Master/Slave ...............................................................5 Units of Measure ....................................................... 21
Semaphore Operation .................................................5 Document History Page ................................................. 22
Maximum Ratings .............................................................7 Sales, Solutions, and Legal Information ...................... 22
Operating Range ...............................................................7 Worldwide Sales and Design Support ....................... 22
Electrical Characteristics .................................................7 Products ....................................................................22
Capacitance ......................................................................8 PSoC Solutions ......................................................... 22
Document #: 001-63982 Rev. *C Page 2 of 22