CY7C1460AV33 CY7C1462AV33 36-Mbit (1 M 36/2 M 18) Pipelined SRAM with NoBL Architecture 36-Mbit (1 M 36/2 M 18) Pipelined SRAM with NoBL Architecture Features Functional Description Pin compatible and functionally equivalent to ZBT The CY7C1460AV33/CY7C1462AV33 are 3.3 V, 1 M 36/2 M 18 synchronous pipelined burst SRAMs with No Bus Latency Supports 250 MHz bus operations with zero wait states (NoBL logic, respectively. They are designed to support Available speed grades are 250, 200 and 167 MHz unlimited true back-to-back read/write operations with no wait states. The CY7C1460AV33/CY7C1462AV33 are equipped with Internally self timed output buffer control to eliminate the need the advanced (NoBL) logic required to enable consecutive to use asynchronous OE read/write operations with data being transferred on every clock Fully registered (inputs and outputs) for pipelined operation cycle. This feature dramatically improves the throughput of data in systems that require frequent write/read transitions. The Byte write capability CY7C1460AV33/CY7C1462AV33 are pin compatible and functionally equivalent to ZBT devices. 3.3 V power supply All synchronous inputs pass through input registers controlled by 3.3 V/2.5 V I/O power supply the rising edge of the clock. All data outputs pass through output Fast clock-to-output times registers controlled by the rising edge of the clock. The clock input is qualified by the clock enable (CEN) signal, which when 2.6 ns (for 250 MHz device) deasserted suspends operation and extends the previous clock Clock enable (CEN) pin to suspend operation cycle. Synchronous self timed writes Write operations are controlled by the byte write selects (BW BW for CY7C1460AV33 and BW BW for a d a b CY7C1460AV33 available in JEDEC-standard Pb-free 100-pin CY7C1462AV33) and a write enable (WE) input. All writes are TQFP and non Pb-free 165-ball FBGA package. conducted with on-chip synchronous self timed write circuitry. CY7C1462AV33 available in JEDEC-standard Pb-free 100-pin TQFP. Three synchronous chip enables (CE , CE , CE ) and an 1 2 3 asynchronous output enable (OE) provide for easy bank IEEE 1149.1 JTAG-compatible boundary scan selection and output tristate control. To avoid bus contention, the output drivers are synchronously tristated during the data portion Burst capability linear or interleaved burst order of a write sequence. ZZ sleep mode option and stop clock option For a complete list of related documentation, click here. Logic Block Diagram CY7C1460AV33 ADDRESS A0, A1, A REGISTER 0 A1 A1 D1 Q1 A0 BURST A0 D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O S U D U T E T A P N P U T U T ADV/LD S A T E WRITE REGISTRY R MEMORY AND DATA COHERENCY B BW a WRITE E S DQ s ARRAY U CONTROL LOGIC DRIVERS G A T DQ Pa BW b I F BW c E DQ Pb M S F BW d DQ Pc T E P E E DQ Pd R R WE S R S I S E N E G INPUT INPUT REGISTER 1 E REGISTER 0 E OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05353 Rev. *N Revised November 14, 2014 CY7C1460AV33 CY7C1462AV33 Logic Block Diagram CY7C1462AV33 ADDRESS A0, A1, A REGISTER 0 A1 A1 D1 Q1 A0 BURST A0 D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O U U T T P S D P U E U ADV/LD A T N T T WRITE REGISTRY S A R MEMORY E B AND DATA COHERENCY BW a WRITE E DQ s U ARRAY S CONTROL LOGIC G DRIVERS A T F DQ Pa I M F BW b E S DQ Pb P E E T S R R E S I R N WE S G E E INPUT INPUT REGISTER 1 E REGISTER 0 E OE READ LOGIC CE1 CE2 CE3 Sleep ZZ Control Document Number: 38-05353 Rev. *N Page 2 of 31