CY7C1463BV33 36-Mbit (2 M 18) Flow-Through SRAM with NoBL Architecture 36-Mbit (2 M 18) Flow-Through SRAM with NoBL Architecture Features Functional Description No Bus Latency (NoBL) architecture eliminates dead The CY7C1463BV33 is a 3.3 V, 2 M 18 Synchronous Flow cycles between write and read cycles -through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of Supports up to 133-MHz bus operations with zero wait states wait states. The CY7C1463BV33 is equipped with the advanced No Data is transferred on every clock Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock Pin-compatible and functionally equivalent to ZBT devices cycle. This feature dramatically improves the throughput of data Internally self timed output buffer control to eliminate the need through the SRAM, especially in systems that require frequent to use OE Write-Read transitions. All synchronous inputs pass through input registers controlled by Registered inputs for flow through operation the rising edge of the clock. The clock input is qualified by the Byte Write capability Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum 3.3 V/2.5 V I/O power supply access delay from the clock rise is 6.5 ns (133-MHz device). Fast clock-to-output times Write operations are controlled by the two or four Byte Write 6.5 ns (for 133-MHz device) Select (BW ) and a Write Enable (WE) input. All writes are X conducted with on-chip synchronous self timed write circuitry. Clock Enable (CEN) pin to enable clock and suspend operation Three synchronous Chip Enables (CE , CE , CE ) and an 1 2 3 Synchronous self timed writes asynchronous Output Enable (OE) provide for easy bank Asynchronous Output Enable selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data CY7C1463BV33 available in JEDEC-standard Pb-free 100-pin portion of a write sequence. TQFP package For a complete list of related documentation, click here. Three chip enables for simple depth expansion Automatic Power down feature available using ZZ mode or CE deselect Burst Capability linear or interleaved burst order Low standby power Selection Guide Description 133 MHz Unit Maximum Access Time 6.5 ns Maximum Operating Current 310 mA Maximum CMOS Standby Current 120 mA Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-75212 Rev. *C Revised January 5, 2016CY7C1463BV33 Logic Block Diagram CY7C1463BV33 ADDRESS A0, A1, A A1 REGISTER A1 D1 Q1 A0 A0 D0 Q0 MODE BURST CE ADV/LD CLK C LOGIC C CEN WRITE ADDRESS REGISTER O U T P D S U A E T T ADV/LD N A S B MEMORY BW A WRITE E U WRITE REGISTRY S ARRAY DQs DRIVERS F BW B AND DATA COHERENCY T DQP A A F E CONTROL LOGIC DQP B M E E P R R S S I WE N E G INPUT E REGISTER OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Document Number: 001-75212 Rev. *C Page 2 of 19