CY7C1470BV33 CY7C1472BV33 CY7C1474BV33 72-Mbit (2M 36/4M 18/1M 72) Pipelined SRAM with NoBL Architecture 72-Mbit (2M 36/4M 18/1M 72) Pipelined SRAM with NoBL Architecture Features Functional Description Pin-compatible and functionally equivalent to ZBT The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are 3.3 V, 2M 36/4M 18/1M 72 Synchronous pipelined burst Supports 250 MHz bus operations with zero wait states SRAMs with No Bus Latency (NoBL) logic, respectively. Available speed grades are 250, 200, and 167 MHz They are designed to support unlimited true back-to-back read or write operations with no wait states. The CY7C1470BV33, Internally self timed output buffer control to eliminate the need CY7C1472BV33, and CY7C1474BV33 are equipped with the to use asynchronous OE advanced (NoBL) logic required to enable consecutive read or Fully registered (inputs and outputs) for pipelined operation write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in Byte Write capability systems that require frequent read or write transitions. The CY7C1470BV33, CY7C1472BV33, and CY7C1474BV33 are pin Single 3.3 V power supply compatible and functionally equivalent to ZBT devices. 3.3 V/2.5 V I/O power supply All synchronous inputs pass through input registers controlled by Fast clock-to-output time the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock 3.0 ns (for 250 MHz device) input is qualified by the Clock Enable (CEN) signal, which when Clock Enable (CEN) pin to suspend operation deasserted suspends operation and extends the previous clock cycle. Synchronous self timed writes Write operations are controlled by the Byte Write Selects CY7C1470BV33, CY7C1472BV33 available in (BW BW for CY7C1470BV33, BW BW for a d a b JEDEC-standard Pb-free 100-pin TQFP, Pb-free and CY7C1472BV33, and BW BW for CY7C1474BV33) and a a h non-Pb-free 165-ball FBGA package. CY7C1474BV33 Write Enable (WE) input. All writes are conducted with on-chip available in Pb-free and non-Pb-free 209-ball FBGA package synchronous self timed write circuitry. IEEE 1149.1 JTAG Boundary Scan compatible Three synchronous Chip Enables (CE , CE , CE ) and an 1 2 3 asynchronous Output Enable (OE) provide for easy bank Burst capability linear or interleaved burst order selection and output tri-state control. To avoid bus contention, ZZ Sleep Mode option and Stop Clock option the output drivers are synchronously tri-stated during the data portion of a write sequence. For a complete list of related documentation, click here. Selection Guide Description 250 MHz 200 MHz 167 MHz Unit Maximum Access Time 3.0 3.0 3.4 ns Maximum Operating Current 500 500 450 mA Maximum CMOS Standby Current 120 120 120 mA Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-15031 Rev. *O Revised February 7, 2018CY7C1470BV33 CY7C1472BV33 CY7C1474BV33 Logic Block Diagram CY7C1470BV33 ADDRESS A0, A1, A REGISTER 0 A1 A1 D1 Q1 A0 BURST A0 D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O S U D U T E T A P N P U T U S T ADV/LD A T E WRITE REGISTRY R MEMORY AND DATA COHERENCY WRITE E S B DQ s BW a ARRAY CONTROL LOGIC G U DRIVERS T DQ Pa BW b A I F BW c E DQ Pb M S F BW d T E DQ Pc E P E R R DQ Pd S WE R S I S E N E G INPUT INPUT E E REGISTER 1 REGISTER 0 OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Logic Block Diagram CY7C1472BV33 ADDRESS A0, A1, A REGISTER 0 A1 A1 D1 Q1 A0 BURST A0 D0 Q0 MODE LOGIC ADV/LD CLK C C CEN WRITE ADDRESS WRITE ADDRESS REGISTER 1 REGISTER 2 O O U U T T P S P D U E A U ADV/LD T N T T WRITE REGISTRY S A R MEMORY E B AND DATA COHERENCY BW a WRITE E DQ s U ARRAY S CONTROL LOGIC G DRIVERS A T F DQ Pa I M F BW b E S DQ Pb P E E T S R R E I S R N WE S G E E INPUT INPUT E E REGISTER 1 REGISTER 0 OE READ LOGIC CE1 CE2 CE3 Sleep ZZ Control Document Number: 001-15031 Rev. *O Page 2 of 35