Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit (2M 36/4M 18/1M 72) Pipelined SRAM with NoBL Architecture 72-Mbit (2M 36/4M 18/1M 72) Pipelined SRAM with NoBL Architecture Features Functional Description Pin compatible and functionally equivalent to ZBT The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are 3.3 V, 2M 36/4M 18/1M 72 synchronous pipelined burst Supports 200 MHz Bus operations with zero wait states SRAMs with No Bus Latency (NoBL) logic, respectively. Available speed grades are 200 and 167 MHz They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1470V33, Internally self timed output buffer control to eliminate the need CY7C1472V33, and CY7C1474V33 are equipped with the to use asynchronous OE advanced (NoBL) logic required to enable consecutive Fully registered (inputs and outputs) for pipelined operation read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data Byte write capability in systems that require frequent write/read transitions. The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are pin Single 3.3 V power supply compatible and functionally equivalent to ZBT devices. 3.3 V/2.5 V I/O power supply All synchronous inputs pass through input registers controlled by Fast clock-to-output time the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock 3.0 ns (for 200 MHz device) input is qualified by the clock enable (CEN) signal, which when Clock enable (CEN) pin to suspend operation deasserted suspends operation and extends the previous clock cycle. Synchronous self timed writes Write operations are controlled by the byte write selects CY7C1470V33 available in JEDEC-standard Pb-free 100-pin (BW BW for CY7C1474V33, BW BW for CY7C1470V33 a h a d TQFP, and non Pb-free 165-ball FBGA package. and BW BW for CY7C1472V33) and a write enable (WE) a b CY7C1472V33 available in JEDEC-standard Pb-free 100-pin input. All writes are conducted with on-chip synchronous self TQFP. CY7C1474V33 available in non Pb-free 209-ball FBGA timed write circuitry. package Three synchronous chip enables (CE , CE , CE ) and an 1 2 3 IEEE 1149.1 JTAG boundary scan compatible asynchronous output enable (OE) provide for easy bank selection and output tristate control. In order to avoid bus Burst capability linear or interleaved burst order contention, the output drivers are synchronously tristated during ZZ sleep mode option and stop clock option the data portion of a write sequence. For a complete list of related documentation, click here. Selection Guide Description 200 MHz 167 MHz Unit Maximum access time 3.0 3.4 ns Maximum operating current 500 450 mA Maximum CMOS standby current 120 120 mA Errata: For information on silicon errata, see Errata on page 35. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05289 Rev. *Y Revised March 28, 2019