CY7C1471BV33 CY7C1473BV33 72-Mbit (2 M 36/4 M 18) Flow-Through SRAM with NoBL Architecture 72-Mbit (2 M 36/4 M 18) Flow-Through SRAM with NoBL Architecture Features Functional Description No bus latency (NoBL) architecture eliminates dead cycles The CY7C1471BV33 and CY7C1473BV33 are 3.3V, between write and read cycles 2M36/4M18 synchronous flow through burst SRAMs designed specifically to support unlimited true back-to-back read Supports up to 133 MHz bus operations with zero wait states or write operations without the insertion of wait states. The CY7C1471BV33 and CY7C1473BV33 are equipped with the Data is transferred on every clock advanced No Bus Latency (NoBL) logic. NoBL is required to Pin compatible and functionally equivalent to ZBT devices enable consecutive read or write operations with data being transferred on every clock cycle. This feature dramatically Internally self timed output buffer control to eliminate the need improves the throughput of data through the SRAM, especially to use OE in systems that require frequent write-read transitions. Registered inputs for flow through operation All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Byte write capability Clock Enable (CEN) signal, which when deasserted suspends 3.3 V/2.5 V I/O supply (V ) DDQ operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133 MHz device). Fast clock-to-output times Write operations are controlled by two or four Byte Write Select 6.5 ns (for 133 MHz device) (BW ) and a Write Enable (WE) input. All writes are conducted X Clock enable (CEN) pin to enable clock and suspend operation with on-chip synchronous self timed write circuitry. Synchronous self-timed writes Three synchronous chip enables (CE , CE , CE ) and an 1 2 3 asynchronous Output Enable (OE) provide for easy bank Asynchronous output enable (OE) selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data CY7C1471BV33 available in JEDEC-standard Pb-free 100-pin portion of a write sequence. thin quad flat pack (TQFP), Pb-free and non-Pb-free 165-ball fine-pitch ball grid array (FBGA) package. CY7C1473BV33 For a complete list of related documentation, click here. available in JEDEC-standard Pb-free 100-pin thin quad flat pack (TQFP) Three chip enables (CE , CE , CE ) for simple depth 1 2 3 expansion Automatic power-down feature available using ZZ mode or CE deselect IEEE 1149.1 JTAG boundary scan compatible Burst capability linear or interleaved burst order Low standby power Selection Guide Description 133 MHz Unit Maximum access time 6.5 ns Maximum operating current 305 mA Maximum CMOS standby current 120 mA Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-15029 Rev. *I Revised November 17, 2014CY7C1471BV33 CY7C1473BV33 Logic Block Diagram CY7C1471BV33 ADDRESS A0, A1, A A1 A1 REGISTER D1 Q1 A0 A0 D0 Q0 MODE BURST CE ADV/LD CLK C LOGIC C CEN WRITE ADDRESS REGISTER O U T P D S U A E T T ADV/LD N A S B MEMORY BW A WRITE E U WRITE REGISTRY S ARRAY DQs DRIVERS F T BW B AND DATA COHERENCY DQP A A F E CONTROL LOGIC DQP B BW C M E E DQP C P R R BW D DQP D S S I WE E N G INPUT E REGISTER OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Logic Block Diagram CY7C1473BV33 ADDRESS A0, A1, A A1 REGISTER A1 D1 Q1 A0 A0 D0 Q0 MODE BURST CE ADV/LD CLK C LOGIC C CEN WRITE ADDRESS REGISTER O U T P D S U A E T T ADV/LD N A S B MEMORY BW A WRITE E U WRITE REGISTRY S ARRAY DQs DRIVERS T F BW B AND DATA COHERENCY DQPA A F E CONTROL LOGIC DQPB M E E P R R S S I WE N E G INPUT E REGISTER OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Document Number: 001-15029 Rev. *I Page 2 of 32