CY7C1471V33 72-Mbit (2M 36) Flow-Through SRAM with NoBL Architecture 72-Mbit (2M 36) Flow-Through SRAM with NoBL Architecture Features Functional Description No Bus Latency (NoBL) architecture eliminates dead The CY7C1471V33 is 3.3 V, 2M 36 synchronous flow through cycles between write and read cycles burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of Supports up to 133 MHz bus operations with zero wait states wait states. The CY7C1471V33 is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Data is transferred on every clock read or write operations with data being transferred on every Pin compatible and functionally equivalent to ZBT devices clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require Internally self timed output buffer control to eliminate the need frequent write-read transitions. to use OE All synchronous inputs pass through input registers controlled by Registered inputs for flow through operation the rising edge of the clock. The clock input is qualified by the clock enable (CEN) signal, which when deasserted suspends Byte Write capability operation and extends the previous clock cycle.Maximum 3.3 V/2.5 V I/O supply (V ) DDQ access delay from the clock rise is 6.5 ns (133-MHz device). Fast clock-to-output times Write operations are controlled by two or four byte write select (BW ) and a write enable (WE) input. All writes are conducted 6.5 ns (for 133-MHz device) X with on-chip synchronous self timed write circuitry. Clock enable (CEN) pin to enable clock and suspend operation Three synchronous chip enables (CE , CE , CE ) and an 1 2 3 Synchronous self timed writes asynchronous output enable (OE) provide for easy bank selection and output tri-state control. To avoid bus contention, Asynchronous output enable (OE) the output drivers are synchronously tri-stated during the data portion of a write sequence. CY7C1471V33 available in JEDEC-standard Pb-free 100-pin TQFP For a complete list of related documentation, click here. Three chip enables (CE , CE , CE ) for simple depth 1 2 3 expansion Automatic power down feature available using ZZ mode or CE deselect Burst capability linear or interleaved burst order Low standby power Selection Guide Description 133 MHz Unit Maximum access time 6.5 ns Maximum operating current 305 mA Maximum CMOS standby current 120 mA Errata: For information on silicon errata, see Errata on page 19. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05288 Rev. *V Revised February 12, 2018CY7C1471V33 Logic Block Diagram CY7C1471V33 ADDRESS A0, A1, A A1 A1 REGISTER D1 Q1 A0 A0 D0 Q0 MODE BURST CE CLK C ADV/LD LOGIC C CEN WRITE ADDRESS REGISTER O U T P D S U A E T T ADV/LD N A S B MEMORY BW A WRITE E U WRITE REGISTRY S ARRAY DQs DRIVERS F BW B T AND DATA COHERENCY DQP A A F E CONTROL LOGIC DQP B BW C M E E DQP C P R R BW D DQP D S S I WE N E G INPUT E REGISTER OE READ LOGIC CE1 CE2 CE3 SLEEP ZZ CONTROL Document Number: 38-05288 Rev. *V Page 2 of 24