Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY7C1470V25 CY7C1472V25 CY7C1474V25 72-Mbit (2M 36/4M 18/1M 72) Pipelined SRAM with NoBL Architecture 72-Mbit (2M 36/4M 18/1M 72) Pipelined SRAM with NoBL Architecture Features Functional Description Pin-compatible and functionally equivalent to ZBT The CY7C1470V25/CY7C1472V25/CY7C1474V25 are 2.5 V, 2M 36/4M 18/1M 72 synchronous pipelined burst SRAMs Supports 200-MHz bus operations with zero wait states with No Bus Latency (NoBL logic, respectively. They are Available speed grades are 200 and 167 MHz designed to support unlimited true back-to-back read/write operations with no wait states. The Internally self-timed output buffer control to eliminate the need CY7C1470V25/CY7C1472V25/CY7C1474V25 are equipped to use asynchronous OE with the advanced (NoBL) logic required to enable consecutive Fully registered (inputs and outputs) for pipelined operation read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data Byte write capability in systems that require frequent write/read transitions. The CY7C1470V25/CY7C1472V25/CY7C1474V25 are pin-compatible Single 2.5 V power supply and functionally equivalent to ZBT devices. 2.5 V I/O supply (V ) DDQ All synchronous inputs pass through input registers controlled by Fast clock-to-output times the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock 3.0 ns (for 200-MHz device) input is qualified by the clock enable (CEN) signal, which when Clock enable (CEN) pin to suspend operation deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects Synchronous self-timed writes (BW BW for CY7C1474V25, BW BW for CY7C1470V25 a h a d CY7C1470V25 available in JEDEC-standard Pb-free 100-pin and BW BW for CY7C1472V25) and a write enable (WE) a b TQFP, Pb-free and non Pb-free 165-ball FBGA package. input. All writes are conducted with on-chip synchronous CY7C1472V25 available in JEDEC-standard Pb-free 100-pin self-timed write circuitry. TQFP. CY7C1474V25 available in Pb-free and non Pb-free Three synchronous chip enables (CE , CE , CE ) and an 1 2 3 209-ball FBGA package asynchronous output enable (OE) provide for easy bank IEEE 1149.1 JTAG boundary scan compatible selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during Burst capability linear or interleaved burst order the data portion of a write sequence. ZZ sleep mode option and stop clock option For a complete list of related documentation, click here. Selection Guide Description 200 MHz 167 MHz Unit Maximum access time 3.0 3.4 ns Maximum operating current 450 400 mA Maximum CMOS standby current 120 120 mA Errata: For information on silicon errata, see Errata on page 36. Details include trigger conditions, devices affected, and proposed workaround Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05290 Rev. *V Revised January 4, 2018