CY7C1470V25
CY7C1472V25
CY7C1474V25
72-Mbit (2 M 36/4 M 18/1 M 72)
Pipelined SRAM with NoBL Architecture
72-Mbit (2 M 36/4 M 18/1 M 72) Pipelined SRAM with NoBLTM Architecture
Features Functional Description
Pin-compatible and functionally equivalent to ZBT The CY7C1470V25/CY7C1472V25/CY7C1474V25 are 2.5 V,
2 M 36/4 M 18/1 M 72 synchronous pipelined burst SRAMs
Supports 200-MHz bus operations with zero wait states
with No Bus Latency (NoBL logic, respectively. They are
Available speed grades are 200 and 167 MHz
designed to support unlimited true back-to-back read/write
operations with no wait states. The
Internally self-timed output buffer control to eliminate the need
CY7C1470V25/CY7C1472V25/CY7C1474V25 are equipped
to use asynchronous OE
with the advanced (NoBL) logic required to enable consecutive
Fully registered (inputs and outputs) for pipelined operation
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
Byte write capability
in systems that require frequent write/read transitions. The
CY7C1470V25/CY7C1472V25/CY7C1474V25 are pin-compatible
Single 2.5 V power supply
and functionally equivalent to ZBT devices.
2.5 V I/O supply (V )
DDQ
All synchronous inputs pass through input registers controlled by
Fast clock-to-output times
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
3.0 ns (for 200-MHz device)
input is qualified by the clock enable (CEN) signal, which when
Clock enable (CEN) pin to suspend operation
deasserted suspends operation and extends the previous clock
cycle. Write operations are controlled by the Byte Write Selects
Synchronous self-timed writes
(BW BW for CY7C1474V25, BW BW for CY7C1470V25
a h a d
CY7C1470V25 available in JEDEC-standard Pb-free 100-pin
and BW BW for CY7C1472V25) and a write enable (WE)
a b
TQFP, Pb-free and non Pb-free 165-ball FBGA package.
input. All writes are conducted with on-chip synchronous
CY7C1472V25 available in JEDEC-standard Pb-free 100-pin
self-timed write circuitry.
TQFP. CY7C1474V25 available in Pb-free and non Pb-free
Three synchronous chip enables (CE , CE , CE ) and an
1 2 3
209-ball FBGA package
asynchronous output enable (OE) provide for easy bank
IEEE 1149.1 JTAG boundary scan compatible selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
Burst capability linear or interleaved burst order
the data portion of a write sequence.
ZZ sleep mode option and stop clock option
For a complete list of related documentation, click here.
Selection Guide
Description 200 MHz 167 MHz Unit
Maximum access time 3.0 3.4 ns
Maximum operating current 450 400 mA
Maximum CMOS standby current 120 120 mA
Errata: For information on silicon errata, see Errata on page 36. Details include trigger conditions, devices affected, and proposed workaround
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 38-05290 Rev. *T Revised November 20, 2014CY7C1470V25
CY7C1472V25
CY7C1474V25
Logic Block Diagram CY7C1470V25
ADDRESS
A0, A1, A
REGISTER 0 A1
A1'
D1 Q1
A0 BURST A0'
D0 Q0
MODE LOGIC
ADV/LD
CLK C
C
CEN
WRITE ADDRESS WRITE ADDRESS
REGISTER 1 REGISTER 2
O
O
S
U
D U
T
E
T
A
P
N P
U T
U
S T
ADV/LD A
T
E
WRITE REGISTRY
R
MEMORY
AND DATA COHERENCY B
BWa WRITE E S DQs
ARRAY
U
CONTROL LOGIC G
DRIVERS A T DQPa
BWb
I
F
BWc E DQPb
M S
F
BWd
T E DQPc
E
P
E
R R DQPd
S
WE R
S
I
S
E N E
G
INPUT INPUT
E E
REGISTER 1 REGISTER 0
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
ZZ
CONTROL
Document Number: 38-05290 Rev. *T Page 2 of 40