CY7C1480BV25 72-Mbit (2 M 36) Pipelined Sync SRAM 72-Mbit (2 M 36) Pipelined Sync SRAM Features Functional Description Supports bus operation up to 250 MHz The CY7C1480BV25 SRAM integrates 2 M 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter Available speed grades are 250, 200, and 167 MHz for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input Registered inputs and outputs for pipelined operation (CLK). The synchronous inputs include all addresses, all data 2.5-V core power supply inputs, address-pipelining Chip Enable (CE ), depth-expansion 1 Chip Enables (CE and CE ), Burst Control inputs (ADSC, 2 3 2.5-V I/O operation ADSP, and ADV), Write Enables (BW , and BWE), and Global X Fast clock-to-output time Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. 3.0 ns (for 250 MHz device) Addresses and chip enables are registered at rising edge of Provide high performance 3-1-1-1 access rate clock when either Address Strobe Processor (ADSP) or Address User selectable burst counter supporting Intel Pentium Strobe Controller (ADSC) is active. Subsequent burst addresses interleaved or linear burst sequences can be internally generated as controlled by the Advance pin (ADV). Separate processor and controller address strobes Address, data inputs, and write controls are registered on-chip Synchronous self timed writes to initiate a self timed Write cycle. This part supports Byte Write operations (see Pin Definitions on page 6 and Truth Table on Asynchronous output enable page 9 for further details). Write cycles can be one to two or four Single cycle chip deselect bytes wide, as controlled by the byte write control inputs. When it is active LOW, GW writes all bytes. CY7C1480BV25 available in JEDEC-standard Pb-free 100-pin For a complete list of related documentation, click here. thin quad flat pack (TQFP), Pb-free and non Pb-free 165-ball fine-pitch ball grid array (FBGA) package. IEEE 1149.1 JTAG-Compatible Boundary Scan ZZ sleep mode option Selection Guide Description 250 MHz 200 MHz 167 MHz Unit Maximum access time 3.0 3.0 3.4 ns Maximum operating current 450 450 400 mA Maximum complementary metal oxide semiconductor (CMOS) standby current 120 120 120 mA Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-15143 Rev. *L Revised November 19, 2014CY7C1480BV25 Logic Block Diagram CY7C1480BV25 A0, A1, A ADDRESS REGISTER 2 A 1:0 MODE Q1 ADV BURST CLK COUNTER CLR AND Q0 LOGIC ADSC ADSP DQD ,DQP D DQ D ,DQPD BYTE BYTE BW D WRITE REGISTER WRITE DRIVER DQC ,DQP C DQC ,DQP C BYTE BW C BYTE OUTPUT WRITE DRIVER OUTPUT WRITE REGISTER MEMORY DQs SENSE BUFFERS ARRAY REGISTERS AMPS DQP A DQB ,DQP B E DQB ,DQP B DQP B BYTE BYTE BW B DQP C WRITE DRIVER WRITE REGISTER DQP D DQA ,DQP A DQA ,DQP A BYTE BYTE BW A WRITE DRIVER WRITE REGISTER BWE INPUT GW REGISTERS ENABLE PIPELINED CE 1 REGISTER ENABLE CE 2 CE 3 OE SLEEP ZZ CONTROL Document Number: 001-15143 Rev. *L Page 2 of 33