CY7C1480V33 72-Mbit (2M 36) Pipelined Sync SRAM 72-Mbit (2M 36) Pipelined Sync SRAM Features Functional Description Supports bus operation up to 200 MHz The CY7C1480V33 SRAM integrates 2M 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter Available speed grades are 200 and 167 MHz for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input Registered inputs and outputs for pipelined operation (CLK). The synchronous inputs include all addresses, all data 3.3 V core power supply inputs, address-pipelining Chip Enable (CE ), depth-expansion 1 Chip Enables (CE and CE ), Burst Control inputs (ADSC, 2 3 2.5 V/3.3 V I/O operation ADSP, and ADV), Write Enables (BW , and BWE), and Global X Fast clock-to-output times Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. 3.0 ns (for 200 MHz device) Addresses and chip enables are registered at the rising edge of Provide high performance 3-1-1-1 access rate the clock when either Address Strobe Processor (ADSP) or User selectable burst counter supporting Intel Pentium Address Strobe Controller (ADSC) are active. Subsequent burst interleaved or linear burst sequences addresses can be internally generated as controlled by the Advance pin (ADV). Separate processor and controller address strobes Address, data inputs, and write controls are registered on-chip Synchronous self timed writes to initiate a self timed write cycle.This part supports byte write operations (seePin Definition on page 5 andTruth Tabl on Asynchronous output enable page 8 for further details). Write cycles can be one to two or four Single cycle chip deselect bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. CY7C1480V33 available in JEDEC-standard Pb-free 100-pin The CY7C1480V33 operates from a +3.3 V core power supply TQFP package while all outputs may operate with either a +2.5 or +3.3 V supply. IEEE 1149.1 JTAG-Compatible Boundary Scan All inputs and outputs are JEDEC standard JESD8-5 compatible. ZZ Sleep Mode option For a complete list of related documentation, click here. Selection Guide Description 200 MHz 167 MHz Unit Maximum Access Time 3.0 3.4 ns Maximum Operating Current 500 450 mA Maximum CMOS Standby Current 120 120 mA Errata: For information on silicon errata, seeErrat on page 21. Details include trigger conditions, devices affected, and proposed workaround. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05283 Rev. *Q Revised August 18, 2017CY7C1480V33 Logic Block Diagram CY7C1480V33 A0, A1, A ADDRESS REGISTER 2 A 1:0 MODE Q1 ADV BURST CLK COUNTER CLR AND Q0 LOGIC ADSC ADSP DQD ,DQP D DQ D ,DQPD BYTE BYTE BW D WRITE REGISTER WRITE DRIVER DQC ,DQP C DQC ,DQP C BYTE BW C BYTE OUTPUT WRITE DRIVER OUTPUT WRITE REGISTER MEMORY SENSE DQs BUFFERS ARRAY REGISTERS AMPS DQP A DQB ,DQP B E DQB ,DQP B DQP B BYTE BYTE BW B DQP C WRITE DRIVER WRITE REGISTER DQP D DQA ,DQP A DQA ,DQP A BYTE BYTE BW A WRITE DRIVER WRITE REGISTER BWE INPUT GW REGISTERS ENABLE PIPELINED CE 1 REGISTER ENABLE CE 2 CE 3 OE SLEEP ZZ CONTROL Document Number: 38-05283 Rev. *Q Page 2 of 26