Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY7C1481BV33 72-Mbit (2M 36) Flow-Through SRAM 72-Mbit (2M 36) Flow-Through SRAM Features Functional Description Supports 133 MHz bus operations The CY7C1481BV33 is a 3.3 V, 2M 36 synchronous flow through SRAM designed to interface with high speed 2M 36 common I/O microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip 3.3 V core power supply (V ) DD counter captures the first address in a burst and increments the 2.5 V or 3.3 V I/O supply (V ) DDQ address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a Fast clock to output time positive edge triggered Clock Input (CLK). The synchronous 6.5 ns (133 MHz version) inputs include all addresses, all data inputs, address pipelining Chip Enable (CE ), depth expansion Chip Enables (CE and Provide high performance 2-1-1-1 access rate 1 2 CE ), Burst Control inputs (ADSC, ADSP, and ADV), Write 3 User selectable burst counter supporting Intel Pentium Enables (BW and BWE), and Global Write (GW). Asynchronous x interleaved or linear burst sequences inputs include the Output Enable (OE) and the ZZ pin. Separate processor and controller address strobes The CY7C1481BV33 enables either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an Synchronous self timed write interleaved burst sequence, while a LOW selects a linear burst Asynchronous output enable sequence. Burst accesses are initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe CY7C1481BV33 available in JEDEC standard Pb-free 100-pin (ADSC) inputs. Address advancement is controlled by the TQFP and 119-ball Pb-free BGA package. Address Advancement (ADV) input. IEEE 1149.1 JTAG compatible boundary scan Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address ZZ sleep mode option Strobe Controller ( ) are active. Subsequent burst ADSC addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1481BV33 operates from a +3.3 V core power supply while all outputs may operate with either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. For a complete list of related documentation, click here. Selection Guide Description 133 MHz Unit Maximum Access Time 6.5 ns Maximum Operating Current 335 mA Maximum CMOS Standby Current 150 mA Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-74857 Rev. *J Revised August 7, 2018