CY7C1480BV33 CY7C1482BV33 72-Mbit (2M 36/4M 18) Pipelined Sync SRAM 72-Mbit (2M 36/4M 18) Pipelined Sync SRAM Features Functional Description Supports bus operation up to 250 MHz The CY7C1480BV33 and CY7C1482BV33 SRAM integrates 2M 36/4M 18 SRAM cells with advanced synchronous Available speed grades are 250, 200, and 167 MHz peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers Registered inputs and outputs for pipelined operation controlled by a positive-edge-triggered Clock Input (CLK). The 3.3 V core power supply synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE ), depth-expansion Chip 1 2.5 V/3.3 V I/O operation Enables (CE and CE ), Burst Control inputs (ADSC, ADSP, and 2 3 Fast clock-to-output times ADV), Write Enables (BW , and BWE), and Global Write (GW). X Asynchronous inputs include the Output Enable (OE) and the ZZ 3.0 ns (for 250 MHz device) pin. Provide high performance 3-1-1-1 access rate Addresses and chip enables are registered at the rising edge of User selectable burst counter supporting Intel Pentium the clock when either address strobe processor (ADSP) or interleaved or linear burst sequences Address Strobe Controller (ADSC) are active. Subsequent burst addresses may be internally generated as controlled by the Separate processor and controller address strobes advance pin (ADV). Synchronous self timed writes Address, data inputs, and write controls are registered on-chip to initiate a self timed write cycle.This part supports byte write Asynchronous output enable operations (see sections Pin Definitions on page 6 and Truth Single cycle chip deselect Table on page 9 for further details). Write cycles can be one to two or four bytes wide as controlled by the byte write control CY7C1480BV33 available in JEDEC-standard Pb-free 100-pin inputs. GW when active LOW causes all bytes to be written. thin quad flat pack (TQFP), Pb-free and non Pb-free 165-ball The CY7C1480BV33 and CY7C1482BV33 operates from a fine-pitch ball grid array (FBGA) package. CY7C1482BV33 +3.3 V core power supply while all outputs may operate with available in non Pb-free 165-ball fine-pitch ball grid array either a +2.5 or +3.3 V supply. All inputs and outputs are JEDEC (FBGA) package standard JESD8-5 compatible. For best practices IEEE 1149.1 JTAG-compatible boundary scan recommendations, refer to the Cypress application note AN1064 SRAM System Guidelines. ZZ sleep mode option For a complete list of related documentation, click here. Selection Guide Description 250 MHz 200 MHz 167 MHz Unit Maximum access time 3.0 3.0 3.4 ns Maximum operating current 500 500 450 mA Maximum CMOS standby current 120 120 120 mA Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-15145 Rev. *L Revised February 15, 2018CY7C1480BV33 CY7C1482BV33 Logic Block Diagram CY7C1480BV33 A0, A1, A ADDRESS REGISTER 2 A 1:0 MODE ADV Q1 BURST CLK COUNTER CLR AND Q0 LOGIC ADSC ADSP DQD ,DQP D DQ D ,DQPD BYTE BYTE BW D WRITE REGISTER WRITE DRIVER DQC ,DQP C DQC ,DQP C BYTE BYTE BW C OUTPUT WRITE REGISTER WRITE DRIVER OUTPUT MEMORY DQs SENSE BUFFERS ARRAY REGISTERS AMPS DQP A DQB ,DQP B E DQB ,DQP B DQP B BYTE BYTE BW B DQP C WRITE DRIVER WRITE REGISTER DQP D DQA ,DQP A DQA ,DQP A BYTE BW A BYTE WRITE DRIVER WRITE REGISTER BWE INPUT GW REGISTERS ENABLE PIPELINED CE 1 REGISTER ENABLE CE 2 CE 3 OE SLEEP ZZ CONTROL Logic Block Diagram CY7C1482BV33 ADDRESS A0, A1, A REGISTER A 1:0 2 MODE Q1 ADV BURST CLK COUNTER AND LOGIC CLR Q0 ADSC ADSP DQ B,DQP B DQ B,DQP B WRITE DRIVER WRITE REGISTER BW B OUTPUT DQs SENSE OUTPUT MEMORY BUFFERS DQP A AMPS ARRAY REGISTERS DQP B DQ A, DQP A E DQ A, DQP A WRITE DRIVER BW A WRITE REGISTER BWE INPUT GW REGISTERS ENABLE CE 1 PIPELINED REGISTER CE2 ENABLE CE3 OE SLEEP ZZ CONTROL Document Number: 001-15145 Rev. *L Page 2 of 34