CY7C1484BV33 72-Mbit (2 M 36) Pipelined DCD Sync SRAM 72-Mbit (2 M 36) Pipelined DCD Sync SRAM Features Functional Description Supports bus operation up to 250 MHz The CY7C1484BV33 SRAM integrates 2 M 36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter Available speed grade is 250 MHz for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input Registered inputs and outputs for pipelined operation (CLK). The synchronous inputs include all addresses, all data Optimal for performance (double cycle deselect) inputs, address pipelining Chip Enable (CE ), depth expansion 1 Chip Enables (CE and CE ), Burst Control inputs (ADSC, 2 3 Depth expansion without wait state ADSP, and ADV), Write Enables (BW , and BWE), and Global X 3.3 V core power supply (V ) Write (GW). Asynchronous inputs include the Output Enable DD (OE) and the ZZ pin. 2.5 V and 3.3 V I/O operation Addresses and chip enables are registered at rising edge of Fast clock to output times clock when either Address Strobe Processor (ADSP) or Address 3.0 ns (for 250 MHz device) Strobe Controller ( ) are active. Subsequent burst ADSC addresses can be internally generated as controlled by the Provide high performance 3-1-1-1 access rate Advance pin (ADV). User selectable burst counter supporting Intel Pentium Address, data inputs, and write controls are registered on-chip interleaved or linear burst sequences to initiate a self timed write cycle. This part supports byte write operations (see Pin Definitions on page 5 and Truth Table on Separate processor and controller address strobes page 8 for more information). Write cycles can be one to four Synchronous self timed writes bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device Asynchronous output enable incorporates an additional pipelined enable register, which delays turning off the output buffers an additional cycle when a CY7C1484BV33 available in Pb-free 165-ball FBGA package deselect is executed. This feature allows depth expansion IEEE 1149.1 JTAG compatible boundary scan without penalizing system performance. ZZ sleep mode option The CY7C1484BV33 operates from a +3.3 V core power supply while all outputs operate with a +3.3 V or a +2.5 V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. Selection Guide Description 250 MHz Unit Maximum Access Time 3.0 ns Maximum Operating Current 500 mA Maximum CMOS Standby Current 120 mA Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-75351 Rev. *B Revised January 9, 2013CY7C1484BV33 Logic Block Diagram CY7C1484BV33 ADDRESS A 0,A1,A REGISTER 2 A 1:0 MODE ADV Q1 BURST CLK COUNTER AND LOGIC CLR Q0 ADSC ADSP DQ D,DQP D DQ D,DQP D BYTE BYTE BW D WRITE REGISTER WRITE DRIVER DQ c,DQP C DQ c,DQP C MEMORY BYTE BW C BYTE ARRAY OUTPUT WRITE DRIVER OUTPUT WRITE REGISTER SENSE DQs BUFFERS REGISTERS AMPS DQP A DQ B,DQP B E DQ B,DQP B DQP B BYTE BYTE BW B DQP C WRITE DRIVER WRITE REGISTER DQP D DQ A, DQP A DQ A, DQP A BYTE BYTE BW A WRITE DRIVER WRITE REGISTER BWE INPUT GW REGISTERS ENABLE PIPELINED CE 1 REGISTER ENABLE CE 2 CE 3 OE SLEEP ZZ CONTROL Document Number: 001-75351 Rev. *B Page 2 of 30