CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 72-Mbit QDR II SRAM 2-Word Burst Architecture Features Configurations Separate Independent Read and Write Data Ports CY7C1510KV18 8M x 8 Supports concurrent transactions CY7C1525KV18 8M x 9 350 MHz Clock for High Bandwidth CY7C1512KV18 4M x 18 CY7C1514KV18 2M x 36 2-word Burst on all Accesses Double Data Rate (DDR) Interfaces on both Read and Write Functional Description Ports (data transferred at 700 MHz) at 350 MHz The CY7C1510KV18, CY7C1525KV18, CY7C1512KV18, and Two Input Clocks (K and K) for precise DDR Timing CY7C1514KV18 are 1.8V Synchronous Pipelined SRAMs, SRAM uses rising edges only equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access Two Input Clocks for Output Data (C and C) to minimize Clock the memory array. The read port has dedicated data outputs to Skew and Flight Time mismatches support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has Echo Clocks (CQ and CQ) simplify Data Capture in High Speed separate data inputs and data outputs to completely eliminate Systems the need to turnaround the data bus that exists with common Single Multiplexed Address Input bus latches Address Inputs I/O devices. Access to each port is through a common address for both Read and Write Ports bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the Separate Port Selects for Depth Expansion QDR II read and write ports are completely independent of one Synchronous internally Self-timed Writes another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is QDR II operates with 1.5 Cycle Read Latency when DOFF is associated with two 8-bit words (CY7C1510KV18), 9-bit words asserted HIGH (CY7C1525KV18), 18-bit words (CY7C1512KV18), or 36-bit Operates similar to QDR I Device with 1 Cycle Read Latency words (CY7C1514KV18) that burst sequentially into or out of the device. Because data can be transferred into and out of the when DOFF is asserted LOW device on every rising edge of both input clocks (K and K and C Available in x8, x9, x18, and x36 Configurations and C), memory bandwidth is maximized while simplifying system design by eliminating bus turnarounds. Full Data Coherency, providing Most Current Data Depth expansion is accomplished with port selects, which Core V = 1.8V (0.1V) I/O V = 1.4V to V DD DDQ DD enables each port to operate independently. Supports both 1.5V and 1.8V I/O supply All synchronous inputs pass through input registers controlled by Available in 165-ball FBGA Package (13 x 15 x 1.4 mm) the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock Offered in both Pb-free and non Pb-free Packages domain) input clocks. Writes are conducted with on-chip Variable Drive HSTL Output Buffers synchronous self-timed write circuitry. JTAG 1149.1 Compatible Test Access Port Phase Locked Loop (PLL) for Accurate Data Placement Table 1. Selection Guide Description 350 MHz 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Unit Maximum Operating Frequency 350 333 300 250 200 167 MHz Maximum Operating Current x8 825 790 730 640 540 480 mA x9 825 790 730 640 540 480 x18 840 810 750 650 550 490 x36 1030 990 910 790 660 580 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-00436 Rev. *J Revised January 29, 2010 + Feedback 4M x 8 Array 4M x 9 Array 4M x 8 Array 4M x 9 Array CY7C1510KV18, CY7C1525KV18 CY7C1512KV18, CY7C1514KV18 Logic Block Diagram (CY7C1510KV18) 8 D 7:0 Write Write 22 Address A Reg Reg (21:0) Register 22 Address A (21:0) Register RPS K Control CLK K Logic Gen. C DOFF Read Data Reg. C CQ 16 V 8 REF 8 CQ Reg. Reg. Control WPS Logic 8 8 NWS Q Reg. 1:0 7:0 8 Logic Block Diagram (CY7C1525KV18) 9 D 8:0 Write Write 22 Address A Reg Reg (21:0) Register 22 Address A (21:0) Register RPS K Control CLK K Logic Gen. C DOFF Read Data Reg. C CQ 18 V 9 REF 9 CQ Reg. Reg. Control WPS Logic 9 9 BWS Q Reg. 0 8:0 9 Document Number: 001-00436 Rev. *J Page 2 of 31 + Feedback Write Add. Decode Write Add. Decode Read Add. Decode Read Add. Decode