CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 72-Mbit QDR II SRAM Four-Word Burst Architecture 72-Mbit QDR II SRAM Four-Word Burst Architecture Features Configurations Separate independent read and write data ports CY7C1526KV18 8M 9 Supports concurrent transactions CY7C1513KV18 4M 18 333 MHz clock for high bandwidth CY7C1515KV18 2M 36 Four-word burst for reducing address bus frequency Functional Description Double data rate (DDR) interfaces on both read and write ports The CY7C1526KV18, CY7C1513KV18, and CY7C1515KV18 (data transferred at 666 MHz) at 333 MHz are 1.8-V synchronous pipelined SRAMs, equipped with QDR II Two input clocks (K and K) for precise DDR timing architecture. QDR II architecture consists of two separate ports: SRAM uses rising edges only the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations Two input clocks for output data (C and C) to minimize clock and the write port has dedicated data inputs to support write skew and flight time mismatches operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to turnaround the Echo clocks (CQ and CQ) simplify data capture in high speed data bus that exists with common I/O devices. Each port can be systems accessed through a common address bus. Addresses for read Single multiplexed address input bus latches address inputs and write addresses are latched on alternate rising edges of the for read and write ports input (K) clock. Accesses to the QDR II read and write ports are independent of one another. To maximize data throughput, both Separate port selects for depth expansion read and write ports are equipped with DDR interfaces. Each Synchronous internally self-timed writes address location is associated with four 9-bit words (CY7C1526KV18), 18-bit words (CY7C1513KV18), or 36-bit QDR II operates with 1.5 cycle read latency when DOFF is words (CY7C1515KV18) that burst sequentially into or out of the asserted HIGH device. Because data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C Operates similar to QDR I device with one cycle read latency and C), memory bandwidth is maximized while simplifying when DOFF is asserted Low system design by eliminating bus turnarounds. Available in 9, 18, and 36 configurations Depth expansion is accomplished with port selects, which Full data coherency, providing most current data enables each port to operate independently. All synchronous inputs pass through input registers controlled by Core V = 1.8 V (0.1 V) I/O V = 1.4 V to V DD DDQ DD the K or K input clocks. All data outputs pass through output Supports both 1.5 V and 1.8 V I/O supply registers controlled by the C or C (or K or K in a single clock Available in 165-ball fine pitch ball grid array (FBGA) package domain) input clocks. Writes are conducted with on-chip (13 15 1.4 mm) synchronous self-timed write circuitry. Offered in both Pb-free and non Pb-free packages For a complete list of related documentation, click here. Variable drive HSTL output buffers JTAG 1149.1 compatible test access port Phase-locked loop (PLL) for accurate data placement Selection Guide Description 333 MHz 300 MHz 250 MHz 200 MHz Unit Maximum operating frequency 333 300 250 200 MHz Maximum operating current 9 600 560 490 Not Offered mA 18 620 570 500 440 36 850 790 680 Not Offered Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-00435 Rev. *W Revised November 17, 20172M x 9 Array 2M x 9 Array 2M x 9 Array 2M x 9 Array CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 Logic Block Diagram CY7C1526KV18 9 D 8:0 Write Write Write Write 21 Address A Reg Reg Reg Reg (20:0) Register 21 Address A (20:0) Register RPS K Control CLK K Logic Gen. C DOFF Read Data Reg. C CQ 36 V 18 REF 9 CQ Reg. Reg. Control 9 WPS Logic 9 9 18 BWS Q Reg. 8:0 0 9 Document Number: 001-00435 Rev. *W Page 2 of 35 Write Add. Decode Read Add. Decode