CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 72-Mbit QDR II SRAM Two-Word Burst Architecture 72-Mbit QDR II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports CY7C1525KV18 8M 9 Supports concurrent transactions CY7C1512KV18 4M 18 350 MHz clock for high bandwidth CY7C1514KV18 2M 36 Two-word burst on all accesses Functional Description Double data rate (DDR) interfaces on both read and write ports The CY7C1525KV18, CY7C1512KV18, and CY7C1514KV18 (data transferred at 700 MHz) at 350 MHz are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: Two input clocks (K and K) for precise DDR timing the read port and the write port to access the memory array. The SRAM uses rising edges only read port has dedicated data outputs to support read operations Two input clocks for output data (C and C) to minimize clock and the write port has dedicated data inputs to support write skew and flight time mismatches operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to turnaround the Echo clocks (CQ and CQ) simplify data capture in high speed data bus that exists with common I/O devices. Access to each systems port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input Single multiplexed address input bus latches address inputs (K) clock. Accesses to the QDR II read and write ports are for both read and write ports completely independent of one another. To maximize data Separate port selects for depth expansion throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with 9-bit words Synchronous internally self-timed writes (CY7C1525KV18), 18-bit words (CY7C1512KV18), or 36-bit QDR II operates with 1.5 cycle read latency when DOFF is words (CY7C1514KV18) that burst sequentially into or out of the asserted HIGH device. Because data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C Operates similar to QDR I device with 1 cycle read latency when and C), memory bandwidth is maximized while simplifying DOFF is asserted LOW system design by eliminating bus turnarounds. Available in 9, 18, and 36 configurations Depth expansion is accomplished with port selects, which Full data coherency, providing most current data enables each port to operate independently. Core V = 1.8 V (0.1 V) I/O V = 1.4 V to V DD DDQ DD All synchronous inputs pass through input registers controlled by Supports both 1.5 V and 1.8 V I/O supply the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock Available in 165-ball fine pitch ball grid array (FBGA) package domain) input clocks. Writes are conducted with on-chip (13 15 1.4 mm) synchronous self-timed write circuitry. Offered in both Pb-free and non Pb-free packages For a complete list of related documentation, click here. Variable drive HSTL output buffers JTAG 1149.1 compatible test access port Phase Locked Loop (PLL) for Accurate Data Placement Selection Guide Description 350 MHz 333 MHz 300 MHz 250 MHz Unit Maximum operating frequency 350 333 300 250 MHz Maximum operating current 9 Not Offered 790 730 640 mA 18 840 810 750 650 36 Not Offered 990 910 790 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-00436 Rev. *V Revised January 19, 20184M x 9 Array 4M x 9 Array CY7C1525KV18 CY7C1512KV18 CY7C1514KV18 Logic Block Diagram CY7C1525KV18 9 D 8:0 Write Write 22 Address A Reg Reg (21:0) Register 22 Address A (21:0) Register RPS K Control CLK K Logic Gen. C DOFF Read Data Reg. C CQ 18 V 9 REF 9 CQ Reg. Reg. Control WPS Logic 9 9 BWS Q Reg. 0 8:0 9 Document Number: 001-00436 Rev. *V Page 2 of 35 Write Add. Decode Read Add. Decode