CY7C1565KV18-400BZI Infineon

CY7C1565KV18 72-Mbit QDR II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 72-QDR II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports With Read Cycle Latency of 2.5 cycles Supports concurrent transactions CY7C1565KV18: 2M 36 550-MHz clock for high bandwidth Functional Description Four-word burst for reducing address bus frequency The CY7C1565KV18 is1.8-V synchronous pipelined SRAM, Double data rate (DDR) Interfaces on both read and write ports equipped with QDR II+ architecture. Similar to QDR II (data transferred at 1100 MHz) at 550 MHz architecture, QDR II+ architecture consists of two separate ports: Available in 2.5-clock cycle latency the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations Two input clocks (K and K) for precise DDR timing and the write port has dedicated data inputs to support write SRAM uses rising edges only operations. QDR II+ architecture has separate data inputs and Echo clocks (CQ and CQ) simplify data capture in high speed data outputs to completely eliminate the need to turnaround the systems data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read Data valid pin (QVLD) to indicate valid data on the output and write addresses are latched on alternate rising edges of the Single multiplexed address input bus latches address inputs input (K) clock. Accesses to the QDR II+ read and write ports are for read and write ports completely independent of one another. To maximize data Separate port selects for depth expansion throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with four 36-bit Synchronous internally self-timed writes words (CY7C1565KV18) that burst sequentially into or out of the Quad data rate (QDR ) II+ operates with 2.5-cycle read latency device. Because data is transferred into and out of the device on when DOFF is asserted HIGH every rising edge of both input clocks (K and K), memory bandwidth is maximized while simplifying system design by Operates similar to QDR I device with one cycle read latency eliminating bus turnarounds. when DOFF is asserted LOW Depth expansion is accomplished with port selects, which Available in 36 configurations enables each port to operate independently. Full data coherency, providing most current data All synchronous inputs pass through input registers controlled by 1 Core V = 1.8 V 0.1 V I/O V = 1.4 V to V the K or K input clocks. All data outputs pass through output DD DDQ DD registers controlled by the K or K input clocks. Writes are Supports both 1.5 V and 1.8 V I/O supply conducted with on-chip synchronous self-timed write circuitry. High-speed transceiver logic (HSTL) inputs and variable drive For a complete list of related documentation, click here. HSTL output buffers Available in 165-ball fine pitch ball grid array (FBGA) package (13 15 1.4 mm) Offered in both Pb-free and non Pb-free packages JTAG 1149.1 compatible test access port Phase-locked loop (PLL) for accurate data placement Selection Guide Description 550 MHz 500 MHz 450 MHz 400 MHz Unit Maximum operating frequency 550 500 450 400 MHz Maximum operating current 36 1310 1210 1100 1000 mA Note 1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V = 1.4 V to V . DDQ DD Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-15878 Rev. *S Revised November 30, 2017512K 36 Array 512K 36 Array 512K 36 Array 512K 36 Array CY7C1565KV18 Logic Block Diagram CY7C1565KV18 36 D 35:0 Write Write Write Write 19 Address A Reg Reg Reg Reg (18:0) Register 19 Address A (18:0) Register RPS K Control CLK K Logic Gen. DOFF Read Data Reg. CQ 144 V 72 REF CQ 36 Reg. Reg. Control WPS 36 Logic 36 72 36 BWS Q Reg. 3:0 35:0 36 QVLD Document Number: 001-15878 Rev. *S Page 2 of 30 Write Add. Decode Read Add. Decode