CY7C1614KV18-333BZC Infineon

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY7C1625KV18 CY7C1612KV18 CY7C1614KV18 144-Mbit QDR II SRAM Two-Word Burst Architecture CY7C1625KV18/CY7C1612KV18/CY7C1614KV18, 144-Mbit QDR II SRAM Two-Word Burst Architecture Features Configurations Separate independent read and write data ports CY7C1625KV18 16M 9 Supports concurrent transactions CY7C1612KV18 8M 18 360-MHz clock for high bandwidth CY7C1614KV18 4M 36 Two-word burst on all accesses Functional Description Double data rate (DDR) interfaces on both read and write ports The CY7C1625KV18, CY7C1612KV18, and CY7C1614KV18 (data transferred at 720 MHz) at 360 MHz are 1.8 V synchronous pipelined SRAMs, equipped with QDR II Two input clocks (K and K) for precise DDR timing architecture. QDR II architecture consists of two separate ports: SRAM uses rising edges only the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations Two input clocks for output data (C and C) to minimize clock and the write port has dedicated data inputs to support write skew and flight time mismatches operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to turn around the Echo clocks (CQ and CQ) simplify data capture in high-speed data bus that exists with common I/O devices. Access to each systems port is through a common address bus. Addresses for read and Single multiplexed address input bus latches address inputs write addresses are latched on alternate rising edges of the input for both read and write ports (K) clock. Accesses to the QDR II read and write ports are completely independent of one another. To maximize data Separate port selects for depth expansion throughput, both read and write ports are equipped with DDR Synchronous internally self-timed writes interfaces. Each address location is associated with two 9-bit words (CY7C1625KV18), 18-bit words (CY7C1612KV18), or Quad data rate (QDR ) II operates with 1.5-cycle read latency 36-bit words (CY7C1614KV18) that burst sequentially into or out when DOFF is asserted high of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks (K and K and Operates similar to QDR I device with 1 cycle read latency when C and C), memory bandwidth is maximized while simplifying DOFF is asserted low system design by eliminating bus turnarounds. Available in 9, 18, and 36 configurations Depth expansion is accomplished with port selects, which Full data coherency, providing most current data enables each port to operate independently. All synchronous inputs pass through input registers controlled by Core V = 1.8 V ( 0.1 V) I/O V = 1.4 V to V DD DDQ DD the K or K input clocks. All data outputs pass through output Supports both 1.5 V and 1.8 V I/O supply registers controlled by the C or C (or K or K in a single clock Available in 165-ball fine-pitch ball grid array (FBGA) package domain) input clocks. Writes are conducted with on-chip (15 17 1.4 mm) synchronous self-timed write circuitry. Offered in both Pb-free and non Pb-free packages For a complete list of related documentation, click here. Variable drive high-speed transceiver logic (HSTL) output buffers JTAG 1149.1 compatible test access port Phase Locked Loop (PLL) for accurate data placement Selection Guide Description 360 MHz 333 MHz 300 MHz 250 MHz Unit Maximum operating frequency 360 333 300 250 MHz Maximum operating current 9 Not Offered 950 880 780 mA 18 1025 970 910 800 36 Not Offered 1160 1080 950 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-16238 Rev. *P Revised May 4, 2020