CY7C1618KV18/CY7C1620KV18 144-Mbit DDR II SRAM Two-Word Burst Architecture 144-Mbit DDR II SRAM Two-Word Burst Architecture Features Configuration 144-Mbit density (8M 18, 4M 36) CY7C1618KV18 8M 18 CY7C1620KV18 4M 36 333 MHz clock for high bandwidth Two-word burst for reducing address bus frequency Functional Description Double data rate (DDR) interfaces (data transferred at The CY7C1618KV18, and CY7C1620KV18 are 1.8-V 666 MHz) at 333 MHz synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced Two input clocks (K and K) for precise DDR timing synchronous peripheral circuitry and a 1-bit burst counter. SRAM uses rising edges only Addresses for read and write are latched on alternate rising Two input clocks for output data (C and C) to minimize clock edges of the input (K) clock. Write data is registered on the rising skew and flight time mismatches edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are Echo clocks (CQ and CQ) simplify data capture in high-speed not provided. On CY7C1618KV18 and CY7C1620KV18, the systems burst counter takes in the least significant bit of the external Synchronous internally self-timed writes address and bursts two 18-bit words in the case of CY7C1618KV18 and two 36-bit words in the case of DDR II operates with 1.5-cycle read latency when DOFF is CY7C1620KV18 sequentially into or out of the device. asserted high Asynchronous inputs include an output impedance matching Operates similar to DDR I device with one cycle read latency input (ZQ). Synchronous data outputs (Q, sharing the same when DOFF is asserted low physical pins as the data inputs D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately 1.8-V core power supply with high-speed transceiver logic capturing data from each individual DDR SRAM in the system (HSTL) inputs and outputs design. Output data clocks (C/C) enable maximum system Variable drive HSTL output buffers clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by Expanded HSTL output voltage (1.4 VV ) DD the K or K input clocks. All data outputs pass through output Supports both 1.5-V and 1.8-V I/O supply registers controlled by the C or C (or K or K in a single clock Available in 165-ball fine-pitch ball grid array (FBGA) package domain) input clocks. Writes are conducted with on-chip (15 17 1.4 mm) synchronous self-timed write circuitry. For a complete list of related documentation, click here. Offered in Pb-free packages JTAG 1149.1 compatible test access port Phase locked loop (PLL) for accurate data placement Selection Guide Description 333 MHz 300 MHz 250 MHz Unit Maximum operating frequency 333 300 250 MHz Maximum operating current 18 650 610 Not Offered mA 36 790 Not Offered 660 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-44274 Rev. *N Revised November 30, 20172M x 36 Array 4M x 18 Array 2M x 36 Array 4M x 18 Array CY7C1618KV18/CY7C1620KV18 Logic Block Diagram CY7C1618KV18 Burst A0 Logic Write Write 23 22 A Reg Reg (22:0) A Address (22:1) Register 18 LD K Output CLK R/W K Logic Gen. Control C DOFF Read Data Reg. C 36 CQ V 18 REF 18 Reg. Reg. Control CQ R/W Logic 18 18 BWS DQ 18 1:0 Reg. 17:0 Logic Block Diagram CY7C1620KV18 Burst A0 Logic Write Write 22 21 A Reg Reg (21:0) A Address (21:1) Register 36 LD K Output CLK R/W K Logic Gen. Control C DOFF Read Data Reg. C 72 CQ V 36 REF 36 Reg. Reg. Control CQ R/W Logic 36 36 BWS DQ 3:0 Reg. 36 35:0 Document Number: 001-44274 Rev. *N Page 2 of 32 Write Add. Decode Write Add. Decode Read Add. Decode Read Add. Decode