CY7C1643KV18/CY7C1645KV18 144-Mbit QDR II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) 144-Mbit QDR II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) JTAG 1149.1 compatible test access port Features Phase locked loop (PLL) for accurate data placement Separate independent read and write data ports Supports concurrent transactions Configurations 450-MHz clock for high bandwidth With Read Cycle Latency of 2.0 cycles: Four-word burst for reducing address bus frequency CY7C1643KV18 8M 18 Double data rate (DDR) interfaces on both read and write ports CY7C1645KV18 4M 36 (data transferred at 900 MHz) at 450 MHz Functional Description Available in 2.0-clock cycle latency Two input clocks (K and K) for precise DDR timing The CY7C1643KV18, and CY7C1645KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II+ SRAM uses rising edges only architecture. Similar to QDR II architecture, QDR II+ architecture Echo clocks (CQ and CQ) simplify data capture in high-speed consists of two separate ports: the read port and the write port to systems access the memory array. The read port has dedicated data outputs to support read operations and the write port has Data valid pin (QVLD) to indicate valid data on the output dedicated data inputs to support write operations. QDR II+ Single multiplexed address input bus latches address inputs architecture has separate data inputs and data outputs to for read and write ports completely eliminate the need to turnaround the data bus that exists with common I/O devices. Each port is accessed through Separate port selects for depth expansion a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Synchronous internally self-timed writes Accesses to the QDR II+ read and write ports are completely Quad data rate (QDR ) II+ operates with 2.0-cycle read latency independent of one another. To maximize data throughput, both when DOFF is asserted high read and write ports are equipped with DDR interfaces. Each address location is associated with four 18-bit words Operates similar to QDR I device with one cycle read latency (CY7C1643KV18), or 36-bit words (CY7C1645KV18) that burst when DOFF is asserted low sequentially into or out of the device. Because data is transferred Available in 18, and 36 configurations into and out of the device on every rising edge of both input clocks (K and K), memory bandwidth is maximized while Full data coherency, providing most current data simplifying system design by eliminating bus turnarounds. 1 Core V = 1.8 V 0.1 V I/O V = 1.4 V to V DD DDQ DD Depth expansion is accomplished with port selects, which Supports both 1.5-V and 1.8-V I/O supply enables each port to operate independently. High-speed transceiver logic (HSTL) Inputs and variable drive All synchronous inputs pass through input registers controlled by HSTL output buffers the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are Available in 165-ball fine pitch ball grid array (FBGA) package conducted with on-chip synchronous self-timed write circuitry. (15 17 1.4 mm) For a complete list of related documentation, click here. Offered in both Pb-free and non Pb-free packages Selection Guide Description 450 MHz 400 MHz Unit Maximum operating frequency 450 400 MHz Maximum operating current 18 940 860 mA 36 1290 1170 Note 1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V = 1.4 V to V . DDQ DD Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-44059 Rev. *N Revised November 28, 20172M x 18 Array 1M x 36 Array 2M x 18 Array 1M x 36 Array 2M x 18 Array 1M x 36 Array 2M x 18 Array 1M x 36 Array CY7C1643KV18/CY7C1645KV18 Logic Block Diagram CY7C1643KV18 18 D 17:0 Write Write Write Write 21 Address A Reg Reg Reg Reg (20:0) Register 21 Address A (20:0) Register RPS K Control CLK K Logic Gen. DOFF Read Data Reg. CQ 72 V 36 REF 18 CQ Reg. Reg. Control 18 WPS Logic 18 18 36 Q BWS Reg. 1:0 17:0 18 QVLD Logic Block Diagram CY7C1645KV18 36 D 35:0 Write Write Write Write 20 Address A Reg Reg Reg Reg (19:0) Register 20 Address A (19:0) Register RPS K Control CLK K Logic Gen. DOFF Read Data Reg. CQ 144 V 72 REF CQ 36 Reg. Reg. Control WPS 36 Logic 36 72 36 BWS Q 3:0 Reg. 35:0 36 QVLD Document Number: 001-44059 Rev. *N Page 2 of 31 Write Add. Decode Write Add. Decode Read Add. Decode Read Add. Decode