CY7C1650KV18-450BZC Infineon

CY7C1648KV18 CY7C1650KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) Phase locked loop (PLL) for accurate data placement Features Configurations 144-Mbit density (8 M 18, 4 M 36) 450-MHz clock for high bandwidth With Read Cycle Latency of 2.0 cycles: Two-word burst for reducing address bus frequency CY7C1648KV18 8 M 18 CY7C1650KV18 4 M 36 Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz Functional Description Available in 2.0-clock cycle latency The CY7C1648KV18, and CY7C1650KV18 are 1.8-V Two input clocks (K and K) for precise DDR timing synchronous pipelined SRAMs equipped with DDR II+ SRAM uses rising edges only architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read Echo clocks (CQ and CQ) simplify data capture in high-speed and write are latched on alternate rising edges of the input (K) systems clock. Write data is registered on the rising edges of both K and Data valid pin (QVLD) to indicate valid data on the output K. Read data is driven on the rising edges of K and K. Each address location is associated with two18-bit words Synchronous internally self-timed writes (CY7C1648KV18), or 36-bit words (CY7C1650KV18) that burst DDR II+ operates with 2.0-cycle read latency when DOFF is sequentially into or out of the device. asserted high Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same Operates similar to DDR I device with one cycle read latency physical pins as the data inputs D) are tightly matched to the two when DOFF is asserted low output echo clocks CQ/CQ, eliminating the need for separately 1 Core V = 1.8 V 0.1 V I/O V = 1.4 V to V DD DDQ DD capturing data from each individual DDR SRAM in the system Supports both 1.5 V and 1.8 V I/O supply design. All synchronous inputs pass through input registers controlled by High-speed transceiver logic (HSTL) inputs and variable drive the K or K input clocks. All data outputs pass through output HSTL output buffers registers controlled by the K or K input clocks. Writes are Available in 165-ball fine-pitch ball grid array (FBGA) package conducted with on-chip synchronous self-timed write circuitry. (15 17 1.4 mm) For a complete list of related documentation, click here. Offered in both Pb-free and non Pb-free packages JTAG 1149.1 compatible test access port Selection Guide Description 450 MHz 400 MHz Unit Maximum operating frequency 450 400 MHz Maximum operating current 18 Not Offered 730 mA 36 980 900 Note 1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V = 1.4 V to V . DDQ DD Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-44061 Rev. *L Revised January 4, 20184M x 18 Array 2M x 36 Array 4M x 18 Array 2M x 36 Array CY7C1648KV18 CY7C1650KV18 Logic Block Diagram CY7C1648KV18 Write Write 22 A Reg Reg (21:0) Address Register 18 LD K Output CLK R/W K Logic Gen. Control DOFF Read Data Reg. 36 CQ V 18 REF 18 Reg. Reg. CQ Control R/W Logic 18 18 BWS 1:0 Reg. 18 DQ 17:0 QVLD Logic Block Diagram CY7C1650KV18 Write Write 21 A Reg (20:0) Reg Address Register 36 LD K Output CLK R/W Logic K Gen. Control DOFF Read Data Reg. 72 CQ V REF 36 36 Reg. Reg. CQ Control R/W Logic 36 36 BWS 3:0 Reg. DQ 36 35:0 QVLD Document Number: 001-44061 Rev. *L Page 2 of 29 Write Add. Decode Write Add. Decode Read Add. Decode Read Add. Decode