Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY7C199D 256-Kbit (32K 8) Static RAM 256-Kbit (32K 8) Static RAM Features Functional Description Temperature range The CY7C199D is a high performance CMOS static RAM organized as 32,768 words by 8-bits. Easy memory expansion is 40 C to 85 C provided by an active LOW chip enable (CE), an active LOW Pin and function compatible with CY7C199C output enable (OE) and tri-state drivers. This device has an automatic power-down feature, reducing the power consumption High speed when deselected. The input and output pins (I/O through I/O ) 0 7 t = 10 ns AA are placed in a high impedance state when the device is Low active power deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). I = 80 mA at 10 ns CC Write to the device by taking chip enable (CE) and write enable Low CMOS standby power (WE) inputs LOW. Data on the eight I/O pins (I/O through I/O ) 0 7 I = 3 mA SB2 is then written into the location specified on the address pins (A 0 2.0 V data retention through A ). 14 Read from the device by taking chip enable (CE) and output Automatic power-down when deselected enable (OE) LOW while forcing write enable (WE) HIGH. Under Complementary metal oxide semiconductor (CMOS) for these conditions, the contents of the memory location specified optimum speed/power by the address pins appears on the I/O pins. Transistor-transistor logic (TTL) compatible inputs and outputs The CY7C199D device is suitable for interfacing with processors that have TTL I/P levels. It is not suitable for processors that Easy memory expansion with CE and OE features require CMOS I/P levels. Please see Electrical Characteristics on page 4 for more details and suggested alternatives. Available in Pb-free 28-pin 300-Mil-wide molded small outline J-lead package (SOJ) and 28-pin thin small outline package For a complete list of related documentation, click here. (TSOP) I packages Logic Block Diagram I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-05471 Rev. *N Revised March 22, 2019