Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY7C2163KV18/CY7C2165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 18-Mbit QDR II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports With Read Cycle Latency of 2.5 cycles: Supports concurrent transactions CY7C2163KV18 1M 18 550-MHz clock for high bandwidth CY7C2165KV18 512K 36 Four-word burst for reducing address bus frequency Functional Description Double data rate (DDR) interfaces on both read and write ports The CY7C2163KV18, and CY7C2165KV18 are 1.8 V (data transferred at 1100 MHz) at 550 MHz synchronous pipelined SRAMs, equipped with QDR II+ Available in 2.5 clock cycle latency architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to Two input clocks (K and K) for precise DDR timing access the memory array. The read port has dedicated data SRAM uses rising edges only outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ Echo clocks (CQ and CQ) simplify data capture in high-speed architecture has separate data inputs and data outputs to systems completely eliminate the need to turnaround the data bus that Data valid pin (QVLD) to indicate valid data on the output exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write addresses On-die termination (ODT) feature are latched on alternate rising edges of the input (K) clock. Supported for D , BWS , and K/K inputs x:0 x:0 Accesses to the QDR II+ read and write ports are completely Single multiplexed address input bus latches address inputs independent of one another. To maximize data throughput, both for read and write ports read and write ports are equipped with DDR interfaces. Each address location is associated with four 18-bit words Separate port selects for depth expansion (CY7C2163KV18), or 36-bit words (CY7C2165KV18) that burst sequentially into or out of the device. Because data is transferred Synchronous internally self-timed writes into and out of the device on every rising edge of both input QDR II+ operates with 2.5 cycle read latency when DOFF is clocks (K and K), memory bandwidth is maximized while asserted HIGH simplifying system design by eliminating bus turn-arounds. Operates similar to QDR I device with one cycle read latency These devices have an ODT feature supported for D , x:0 when DOFF is asserted LOW BWS , and K/K inputs, which helps eliminate external x:0 termination resistors, reduce cost, reduce board area, and Available in 18 and 36 configurations simplify board routing. Full data coherency, providing most current data Depth expansion is accomplished with port selects, which 1 enables each port to operate independently. Core V = 1.8 V 0.1 V I/O V = 1.4 V to V DD DDQ DD All synchronous inputs pass through input registers controlled by Supports both 1.5 V and 1.8 V I/O supply the K or K input clocks. All data outputs pass through output HSTL inputs and variable drive HSTL output buffers registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Available in 165-ball FBGA package (13 15 1.4 mm) For a complete list of related resources, click here. CY7C2163KV18 offered in Pb-free packages and CY7C2165KV18 offered in non Pb-free packages JTAG 1149.1 compatible test access port Phase-locked loop (PLL) for accurate data placement Selection Guide Description 550 MHz 450 MHz Unit Maximum operating frequency 550 450 MHz Maximum operating current 18 780 670 mA 36 1100 930 Note 1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V = 1.4 V to V . DDQ DD Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-58921 Rev. *K Revised January 4, 2018