CY7C2168KV18/CY7C2170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations 18-Mbit density (1M 18, 512K 36) With Read Cycle Latency of 2.5 cycles: CY7C2168KV18 1M 18 550-MHz clock for high bandwidth CY7C2170KV18 512K 36 Two-word burst for reducing address bus frequency Double data rate (DDR) interfaces (data transferred at Functional Description 1100 MHz) at 550 MHz The CY7C2168KV18, and CY7C2170KV18 are 1.8 V Available in 2.5 clock cycle latency Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with Two input clocks (K and K) for precise DDR timing advanced synchronous peripheral circuitry. Addresses for read SRAM uses rising edges only and write are latched on alternate rising edges of the input (K) Echo clocks (CQ and CQ) simplify data capture in high-speed clock. Write data is registered on the rising edges of both K and systems K. Read data is driven on the rising edges of K and K. Each address location is associated with two 18-bit words Data valid pin (QVLD) to indicate valid data on the output (CY7C2168KV18), or 36-bit words (CY7C2170KV18) that burst sequentially into or out of the device. On-die termination (ODT) feature Supported for D , BWS , and K/K inputs These devices have an ODT feature supported for D , x:0 x:0 x:0 BWS , and K/K inputs, which helps eliminate external x:0 Synchronous internally self-timed writes termination resistors, reduce cost, reduce board area, and simplify board routing. DDR II+ operates with 2.5 cycle read latency when DOFF is asserted HIGH Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same Operates similar to DDR I device with one cycle read latency physical pins as the data inputs D) are tightly matched to the two when DOFF is asserted LOW output echo clocks CQ/CQ, eliminating the need for separately 1 Core V = 1.8 V 0.1 V I/O V = 1.4 V to V capturing data from each individual DDR SRAM in the system DD DDQ DD design. Supports both 1.5 V and 1.8 V I/O supply All synchronous inputs pass through input registers controlled by HSTL inputs and variable drive HSTL output buffers the K or K input clocks. All data outputs pass through output Available in 165-ball FBGA package (13 15 1.4 mm) registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. CY7C2168KV18 offered in non Pb-free packages and CY7C2170KV18 offered in both Pb-free and non Pb-free For a complete list of related resources, click here. packages JTAG 1149.1 compatible test access port Phase locked loop (PLL) for accurate data placement Selection Guide Description 550 MHz 450 MHz 400 MHz Unit Maximum operating frequency 550 450 400 MHz Maximum operating current 18 650 560 Not Offered mA 36 820 Not Offered 640 Note 1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V = 1.4 V to V . DDQ DD Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-58923 Rev. *J Revised January 4, 2018512K x 18 Array 256K x 36 Array 512K x 18 Array 256K x 36 Array CY7C2168KV18/CY7C2170KV18 Logic Block Diagram CY7C2168KV18 Write Write 19 A Reg (18:0) Reg Address Register 18 LD K Output CLK R/W Logic K Gen. Control DOFF Read Data Reg. 36 CQ V 18 REF 18 Reg. Reg. CQ Control R/W Logic 18 18 BWS 1:0 Reg. DQ 18 17:0 QVLD Logic Block Diagram CY7C2170KV18 Write Write 18 A (17:0) Reg Reg Address Register 36 LD K Output CLK R/W Logic K Gen. Control DOFF Read Data Reg. 72 CQ V 36 REF 36 Reg. Reg. CQ Control R/W Logic 36 36 BWS 3:0 Reg. 36 DQ 35:0 QVLD Document Number: 001-58923 Rev. *J Page 2 of 31 Write Add. Decode Write Add. Decode Read Add. Decode Read Add. Decode