Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY7C2268KV18/CY7C2270KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations 36-Mbit density (2M 18, 1M 36) With Read Cycle Latency of 2.5 Cycles: CY7C2268KV18 2M 18 550 MHz clock for high bandwidth CY7C2270KV18 1M 36 Two-word burst for reducing address bus frequency Double data rate (DDR) interfaces (data transferred at Functional Description 1100 MHz) at 550 MHz The CY7C2268KV18, and CY7C2270KV18 are 1.8 V Available in 2.5 clock cycle latency synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with Two input clocks (K and K) for precise DDR timing advanced synchronous peripheral circuitry. Addresses for read SRAM uses rising edges only and write are latched on alternate rising edges of the input (K) Echo clocks (CQ and CQ) simplify data capture in high speed clock. Write data is registered on the rising edges of both K and systems K. Read data is driven on the rising edges of K and K. Each address location is associated with two 18-bit words Data valid pin (QVLD) to indicate valid data on the output (CY7C2268KV18), or 36-bit words (CY7C2270KV18) that burst sequentially into or out of the device. On-die termination (ODT) feature Supported for D , BWS , and K/K inputs These devices have an on-die termination feature supported for x:0 x:0 D , BWS , and K/K inputs, which helps eliminate external x:0 x:0 Synchronous internally self-timed writes termination resistors, reduce cost, reduce board area, and simplify board routing. DDR II+ operates with 2.5 cycle read latency when DOFF is asserted HIGH Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same Operates similar to DDR I device with 1 cycle read latency when physical pins as the data inputs D) are tightly matched to the two DOFF is asserted LOW output echo clocks CQ/CQ, eliminating the need for separately 1 Core V = 1.8 V 0.1 V I/O V = 1.4 V to V capturing data from each individual DDR SRAM in the system DD DDQ DD design. Supports both 1.5 V and 1.8 V I/O supply All synchronous inputs pass through input registers controlled by HSTL inputs and variable drive HSTL output buffers the K or K input clocks. All data outputs pass through output Available in 165-ball FBGA package (13 15 1.4 mm) registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Offered in both Pb-free and non Pb-free packages For a complete list of related documentation, click here. JTAG 1149.1 compatible test access port Phase-locked loop (PLL) for accurate data placement Selection Guide Description 550 MHz 450 MHz 400 MHz Unit Maximum operating frequency 550 450 400 MHz Maximum operating current 18 700 600 Not Offered mA 36 890 Not Offered 690 Note 1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V = 1.4 V to V . DDQ DD Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-57845 Rev. *I Revised January 4, 2018