CY7C25442KV18 72-Mbit QDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 72-Mbit QDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT JTAG 1149.1 compatible test access port Features Phase Locked Loop (PLL) for accurate data placement Separate independent read and write data ports Supports concurrent transactions Configurations 333-MHz clock for high bandwidth With Read Cycle Latency of 2.0 cycles: Two-word burst for reducing address bus frequency CY7C25442KV18 2M 36 Double data rate (DDR) interfaces on both read and write ports Functional Description (data transferred at 666 MHz) at 333 MHz The CY7C25442KV18 are 1.8-V synchronous pipelined SRAMs, Available in 2.0 clock cycle latency equipped with QDR II+ architecture. Similar to the QDRII Two input clocks (K and K) for precise DDR timing architecture, QDR II+ architecture consists of two separate ports: SRAM uses rising edges only the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations Echo clocks (CQ and CQ) simplify data capture in high speed and the write port has dedicated data inputs to support write systems operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to turn around Data valid pin (QVLD) to indicate valid data on the output the data bus that exists with common devices. Access to each On-die termination (ODT) feature port is through a common address bus. Addresses for read and Supported for D , BWS , and K/K inputs write addresses are latched on alternate rising edges of the input x:0 x:0 (K) clock. Accesses to the QDR II+ read and write ports are Single multiplexed address input bus latches address inputs independent of one another. To maximize data throughput, both for both read and write ports read and write ports are equipped with DDR interfaces. Each Separate port selects for depth expansion address location is associated with two 36-bit words (CY7C25442KV18) that burst sequentially into or out of the Synchronous internally self-timed writes device. Because data can be transferred into and out of the device on every rising edge of both input clocks (K and K), QDR II+ operates with 2.0 cycle read latency when DOFF is memory bandwidth is maximized while simplifying system asserted HIGH design by eliminating bus turnarounds. Operates similar to QDR I device with 1 cycle read latency when These devices have an on-die termination feature supported for DOFF is asserted LOW D , BWS , and K/K inputs, which helps eliminate external x:0 x:0 Available in 36 configurations termination resistors, reduce cost, reduce board area, and simplify board routing. Full data coherency, providing most current data Depth expansion is accomplished with port selects, which 1 Core V = 1.8 V 0.1 V V = 1.4 V to V DD DDQ DD enables each port to operate independently. Supports both 1.5 V and 1.8 V supply All synchronous inputs pass through input registers controlled by HSTL inputs and variable drive HSTL output buffers the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are Available in 165-ball FBGA package (13 15 1.4 mm) conducted with on-chip synchronous self-timed write circuitry. Offered in both Pb-free and non Pb-free packages For a complete list of related documentation, click here. Selection Guide Description 333 MHz 300 MHz Unit Maximum operating frequency 333 300 MHz Maximum operating current 36 990 910 mA Note 1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V = 1.4 V to V . DDQ DD Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-66481 Rev. *G Revised November 23, 20171M x 36 Array 1M x 36 Array CY7C25442KV18 Logic Block Diagram CY7C25442KV18 36 D 35:0 Write Write 20 Address A Reg Reg (19:0) Register 20 Address A (19:0) Register RPS K Control CLK K Logic Gen. DOFF Read Data Reg. CQ 72 V 36 REF CQ 36 Reg. Reg. Control WPS Logic 36 36 BWS Q 3:0 Reg. 35:0 36 QVLD Document Number: 001-66481 Rev. *G Page 2 of 28 Write Add. Decode Read Add. Decode