CY7C2562XV18/CY7C2564XV18 72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports With Read Cycle Latency of 2.5 cycles: Supports concurrent transactions CY7C2562XV18 4M 18 450 MHz clock for high bandwidth CY7C2564XV18 2M 36 Two-word burst for reducing address bus frequency Functional Description Double data rate (DDR) interfaces on both read and write ports The CY7C2562XV18 and CY7C2564XV18 are 1.8V (data transferred at 900 MHz) at 450 MHz Synchronous Pipelined SRAMs, equipped with QDR-II+ architecture. Similar to QDR II architecture, QDR II+ architecture Available in 2.5 clock cycle latency consists of two separate ports: the read port and the write port to Two input clocks (K and K) for precise DDR timing access the memory array. The read port has dedicated data outputs to support read operations and the write port has SRAM uses rising edges only dedicated data inputs to support write operations. QDR II+ Echo clocks (CQ and CQ) simplify data capture in high-speed architecture has separate data inputs and data outputs to systems completely eliminate the need to turnaround the data bus that exists with common devices. Access to each port is through a Data valid pin (QVLD) to indicate valid data on the output common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. On-Die Termination (ODT) feature Accesses to the QDR II+ read and write ports are completely Supported for D , BWS , and K/K inputs x:0 x:0 independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each Single multiplexed address input bus latches address inputs address location is associated with two 18-bit words for both read and write ports (CY7C2562XV18), or 36-bit words (CY7C2564XV18) that burst Separate port selects for depth expansion sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both Synchronous internally self-timed writes input clocks (K and K), memory bandwidth is maximized while simplifying system design by eliminating bus turnarounds. QDR-II+ Xtreme operates with 2.5 cycle read latency when DOFF is asserted HIGH These devices have an on-die termination (ODT) feature supported for D , BWS , and K/K inputs, which helps x:0 x:0 Operates similar to QDR I device with 1 cycle read latency when eliminate external termination resistors, reduce cost, reduce DOFF is asserted LOW board area, and simplify board routing. Available in 18, and 36 configurations Depth expansion is accomplished with port selects, which enables each port to operate independently. Full data coherency, providing most current data All synchronous inputs pass through input registers controlled by Core V = 1.8 V 0.1 V V = 1.4 V to 1.6 V DD DDQ the K or K input clocks. All data outputs pass through output Supports 1.5 V I/O supply registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. HSTL inputs and variable drive HSTL output buffers For a complete list of related documentation, click here. Available in 165-ball FBGA package (13 15 1.4 mm) CY7C2564XV18 offered in both Pb-free and non Pb-free packages and CY7C2562XV18 offered in Pb-free package only. JTAG 1149.1 compatible test access port Phase-locked loop (PLL) for accurate data placement Selection Guide Description 450 MHz 366 MHz Unit Maximum Operating Frequency 450 366 MHz Maximum Operating Current 18 1205 970 mA 36 1445 1165 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-70204 Rev. *G Revised August 21, 20172M x 18 Array 1M x 36 Array 2M x 18 Array 1M x 36 Array CY7C2562XV18/CY7C2564XV18 Logic Block Diagram CY7C2562XV18 18 D 17:0 Write Write 21 Address A Reg Reg (20:0) Register 21 Address A (20:0) Register RPS K Control CLK K Logic Gen. DOFF Read Data Reg. CQ 36 V 18 REF 18 CQ Reg. Reg. Control WPS Logic 18 18 BWS Q Reg. 1:0 17:0 18 QVLD Logic Block Diagram CY7C2564XV18 36 D 35:0 Write Write 20 Address A Reg Reg (19:0) Register 20 Address A (19:0) Register RPS K Control CLK K Logic Gen. DOFF Read Data Reg. CQ 72 V 36 REF 36 CQ Reg. Reg. Control WPS Logic 36 36 BWS Q Reg. 3:0 35:0 36 QVLD Document Number: 001-70204 Rev. *G Page 2 of 29 Write Add. Decode Write Add. Decode Read Add. Decode Read Add. Decode