CY7C2563XV18/CY7C2565XV18 72-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 72-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations Separate independent read and write data ports With Read Cycle Latency of 2.5 cycles Supports concurrent transactions CY7C2563XV18 4M 18 633 MHz clock for high bandwidth CY7C2565XV18 2M 36 Four-word burst for reducing address bus frequency Functional Description Double data rate (DDR) interfaces on both read and write ports The CY7C2563XV18 and CY7C2565XV18 are 1.8V (data transferred at 1266 MHz) at 633 MHz Synchronous Pipelined SRAMs, equipped with QDR II+ Available in 2.5 clock cycle latency architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to Two input clocks (K and K) for precise DDR timing access the memory array. The read port has dedicated data SRAM uses rising edges only outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ Echo clocks (CQ and CQ) simplify data capture in high-speed architecture has separate data inputs and data outputs to systems completely eliminate the need to turn-around the data bus that Data valid pin (QVLD) to indicate valid data on the output exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write addresses On-die termination (ODT) feature are latched on alternate rising edges of the input (K) clock. Supported for D , BWS , and K/K inputs x:0 x:0 Accesses to the QDR II+ Xtreme read and write ports are Single multiplexed address input bus latches address inputs completely independent of one another. To maximize data for read and write ports throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with four 18-bit Separate port selects for depth expansion words (CY7C2563XV18), or 36-bit words (CY7C2565XV18) that burst sequentially into or out of the device. Because data is Synchronous internally self-timed writes transferred into and out of the device on every rising edge of both QDR II+ Xtreme operates with 2.5 cycle read latency when input clocks (K and K), memory bandwidth is maximized while DOFF is asserted HIGH simplifying system design by eliminating bus turn-arounds. Operates similar to QDR I device with 1 cycle read latency when These devices have an on-die termination feature supported for DOFF is asserted LOW D , BWS , and K/K inputs, which helps eliminate external x:0 x:0 termination resistors, reduce cost, reduce board area, and Available in 18, and 36 configurations simplify board routing. Full data coherency, providing most current data Depth expansion is accomplished with port selects, which enables each port to operate independently. Core V = 1.8 V 0.1 V I/O V = 1.4 V to 1.6 V DD DDQ All synchronous inputs pass through input registers controlled by Supports 1.5 V I/O supply the K or K input clocks. All data outputs pass through output HSTL inputs and variable drive HSTL output buffers registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Available in 165-ball FBGA package (13 15 1.4 mm) For a complete list of related documentation, click here. Offered in both Pb-free and non Pb-free packages JTAG 1149.1 compatible test access port Phase-locked loop (PLL) for accurate data placement Selection Guide Description 633 MHz 600 MHz Unit Maximum Operating Frequency 633 600 MHz Maximum Operating Current 18 1165 1100 mA 36 1660 1570 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-68997 Rev. *G Revised November 23, 20171M x 18 Array 512K x 36 Array 1M x 18 Array 512K x 36 Array 1M x 18 Array 512K x 36 Array 1M x 18 Array 512K x 36 Array CY7C2563XV18/CY7C2565XV18 Logic Block Diagram CY7C2563XV18 18 D 17:0 Write Write Write Write 20 Address A Reg Reg Reg Reg (19:0) Register 20 Address A (19:0) Register RPS K Control CLK K Logic Gen. DOFF Read Data Reg. CQ 72 V 36 REF 18 CQ Reg. Reg. Control 18 WPS Logic 18 18 36 Q BWS Reg. 1:0 17:0 18 QVLD Logic Block Diagram CY7C2565XV18 36 D 35:0 Write Write Write Write 19 Address A Reg Reg Reg Reg (18:0) Register 19 Address A (18:0) Register RPS K Control CLK K Logic Gen. DOFF Read Data Reg. CQ 144 V 72 REF CQ 36 Reg. Reg. Control WPS 36 Logic 36 72 36 BWS Q Reg. 3:0 35:0 36 QVLD Document Number: 001-68997 Rev. *G Page 2 of 29 Write Add. Decode Write Add. Decode Read Add. Decode Read Add. Decode