CY7C2642KV18/CY7C2644KV18 144-Mbit QDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 144-Mbit QDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT Phase Locked Loop (PLL) for accurate data placement Features Configurations Separate independent read and write data ports Supports concurrent transactions With Read Cycle Latency of 2.0 cycles: 333-MHz clock for high bandwidth CY7C2642KV18 8 M 18 Two-word burst for reducing address bus frequency CY7C2644KV18 4 M 36 Double data rate (DDR) interfaces on both read and write ports Functional Description (data transferred at 666 MHz) at 333 MHz Available in 2.0-clock cycle latency The CY7C2642KV18, and CY7C2644KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II+ Two input clocks (K and K) for precise DDR timing architecture. Similar to QDR II architecture, QDR II+ architecture SRAM uses rising edges only consists of two separate ports: the read port and the write port to Echo clocks (CQ and CQ) simplify data capture in high-speed access the memory array. The read port has dedicated data systems outputs to support read operations and the write port has dedicated data inputs to support write operations. QDRII+ Data valid pin (QVLD) to indicate valid data on the output architecture has separate data inputs and data outputs to On-die termination (ODT) feature completely eliminate the need to turn around the data bus that Supported for D , BWS , and K/K inputs x:0 x:0 exists with common I/O devices. Access to each port is through Single multiplexed address input bus latches address inputs a common address bus. Addresses for read and write addresses for both read and write ports are latched on alternate rising edges of the input (K) clock. Accesses to the QDR II+ read and write ports are completely Separate port selects for depth expansion independent of one another. To maximize data throughput, both Synchronous internally self-timed writes read and write ports are equipped with DDR interfaces. Each address location is associated with two 18-bit words Quad data rate (QDR ) II+ operates with 2.0-cycle read latency (CY7C2642KV18), or 36-bit words (CY7C2644KV18) that burst when DOFF is asserted high sequentially into or out of the device. Because data can be Operates similar to QDR I device with one cycle read latency transferred into and out of the device on every rising edge of both when DOFF is asserted low input clocks (K and K), memory bandwidth is maximized while simplifying system design by eliminating bus turn arounds. Available in 18, and 36 configurations These devices have an ODT feature supported for D , x:0 Full data coherency, providing most current data BWS , and K/K inputs, which helps eliminate external x:0 1 termination resistors, reduce cost, reduce board area, and Core V = 1.8 V 0.1 V I/O V = 1.4 V to V DD DDQ DD simplify board routing. Supports both 1.5 V and 1.8 V I/O supply Depth expansion is accomplished with port selects, which High-speed transceiver logic (HSTL) inputs and variable drive enables each port to operate independently. HSTL output buffers All synchronous inputs pass through input registers controlled by Available in 165-ball fine pitch ball grid array (FBGA) package the K or K input clocks. All data outputs pass through output (15 17 1.4 mm) registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Offered in both Pb-free and non Pb-free packages For a complete list of related documentation, click here. JTAG 1149.1 compatible test access port Selection Guide Description 333 MHz 300 MHz Unit Maximum operating frequency 333 300 MHz Maximum operating current 18 970 Not Offered mA 36 1160 1080 Note 1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V = 1.4 V to V . DDQ DD Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-44138 Rev. *P Revised December 31, 20154M x 18 Array 2M x 36 Array 4M x 18 Array 2M x 36 Array CY7C2642KV18/CY7C2644KV18 Logic Block Diagram CY7C2642KV18 18 D 17:0 Write Write 22 Address A Reg Reg (21:0) Register 22 Address A (21:0) Register RPS K Control CLK K Logic Gen. DOFF Read Data Reg. CQ 36 V 18 REF CQ 18 Reg. Reg. Control WPS Logic 18 18 BWS Q Reg. 17:0 1:0 18 QVLD Logic Block Diagram CY7C2644KV18 36 D 35:0 Write Write 21 Address A Reg Reg (20:0) Register 21 Address A (20:0) Register RPS K Control CLK K Logic Gen. DOFF Read Data Reg. CQ 72 V 36 REF 36 CQ Reg. Reg. Control WPS Logic 36 36 Q BWS Reg. 3:0 35:0 36 QVLD Document Number: 001-44138 Rev. *P Page 2 of 30 Write Add. Decode Write Add. Decode Read Add. Decode Read Add. Decode