CY7C2670KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Features Configurations 144-Mbit density (4 M 36) With Read Cycle Latency of 2.5 cycles: CY7C2670KV18 4 M 36 550-MHz clock for high bandwidth Two-word burst for reducing address bus frequency Functional Description Double data rate (DDR) interfaces (data transferred at The CY7C2670KV18 is 1.8-V synchronous pipelined SRAM 1100 MHz) at 550 MHz equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Available in 2.5 clock cycle latency Addresses for read and write are latched on alternate rising Two input clocks (K and K) for precise DDR timing edges of the input (K) clock. Write data is registered on the rising SRAM uses rising edges only edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 36-bit Echo clocks (CQ and CQ) simplify data capture in high-speed words (CY7C2670KV18) that burst sequentially into or out of the systems device. Data valid pin (QVLD) to indicate valid data on the output These devices have an ODT feature supported for D , x:0 BWS , and K/K inputs, which helps eliminate external On-die termination (ODT) feature x:0 termination resistors, reduce cost, reduce board area, and Supported for D , BWS , and K/K inputs x:0 x:0 simplify board routing. Synchronous internally self-timed writes Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same DDR II+ operates with 2.5-cycle read latency when DOFF is physical pins as the data inputs D) are tightly matched to the two asserted high output echo clocks CQ/CQ, eliminating the need for separately Operates similar to DDR I device with 1 cycle read latency when capturing data from each individual DDR SRAM in the system DOFF is asserted low design. 1 Core V = 1.8 V 0.1 V I/O V = 1.4 V to V All synchronous inputs pass through input registers controlled by DD DDQ DD the K or K input clocks. All data outputs pass through output Supports both 1.5 V and 1.8 V I/O supply registers controlled by the K or K input clocks. Writes are High-speed transceiver logic (HSTL) inputs and variable drive conducted with on-chip synchronous self-timed write circuitry. HSTL output buffers For a complete list of related documentation, click here. Available in 165-ball fine-pitch ball grid array (FBGA) package (15 17 1.4 mm) Offered in non Pb-free package. JTAG 1149.1 compatible test access port Phase locked loop (PLL) for accurate data placement Selection Guide Description 550 MHz 450 MHz Unit Maximum operating frequency 550 450 MHz Maximum operating current 36 1140 980 mA Note 1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V = 1.4 V to V . DDQ DD Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-44143 Rev. *M Revised January 4, 20182M x 36 Array 2M x 36 Array CY7C2670KV18 Logic Block Diagram CY7C2670KV18 Write Write 21 A Reg (20:0) Reg Address Register 36 LD K Output CLK R/W Logic K Gen. Control DOFF Read Data Reg. 72 CQ V 36 REF 36 Reg. Reg. CQ Control R/W Logic 36 36 BWS 3:0 Reg. DQ 36 35:0 QVLD Document Number: 001-44143 Rev. *M Page 2 of 29 Write Add. Decode Read Add. Decode