CY7S1041G CY7S1041GE 4-Mbit (256K words 16 bit) Static RAM with PowerSnooze and Error Correcting Code (ECC) 4-Mbit (256K words 16 bit) Static RAM with PowerSnooze and Error Correcting Code (ECC) Deep-Sleep input (DS) must be deasserted HIGH for normal Features operating mode. High speed To perform data writes, assert the Chip Enable (CE) and Write Access time (t ) = 10 ns / 15 ns AA Enable (WE) inputs LOW, and provide the data and address on Ultra-low power Deep-Sleep (DS) current device data pins (I/O through I/O ) and address pins (A 0 15 0 I = 15 A through A ) respectively. The Byte High Enable (BHE) and Byte DS 17 Low Enable (BLE) inputs control byte writes, and write data on Low active and standby currents the corresponding I/O lines to the memory location specified. Active Current I = 38-mA typical CC BHE controls I/O through I/O and BLE controls I/O through 8 15 0 Standby Current I = 6-mA typical SB2 I/O . 7 Wide operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, To perform data reads, assert the Chip Enable (CE) and Output 4.5 V to 5.5 V Enable (OE) inputs LOW and provide the required address on 1 Embedded ECC for single-bit error correction the address lines. Read data is accessible on the I/O lines (I/O 0 through I/O ). You can perform byte accesses by asserting the 1.0-V data retention 15 required byte enable signal (BHE or BLE) to read either the TTL- compatible inputs and outputs upper byte or the lower byte of data from the specified address location Error indication (ERR) pin to indicate 1-bit error detection and correction The device is placed in a low-power Deep-Sleep mode when the Deep-Sleep input (DS) is asserted LOW. In this state, the device Available in Pb-free 44-pin TSOP II, 44-SOJ and 48-ball VFBGA is disabled for normal operation and is placed in a low power data retention mode. The device can be activated by deasserting the Functional Description Deep-Sleep input (DS) to HIGH. The CY7S1041G is a high-performance PowerSnooze static The CY7S1041G is available in 44-pin TSOP II, 48-ball VFBGA RAM organized as 256K words 16 bits. This device features and 44-pin (400-mil) Molded SOJ. fast access times (10 ns) and a unique ultra-low power Deep-Sleep mode. With Deep-Sleep mode currents as low as 15 A, the CY7S1041G/ CY7S1041GE devices combine the best features of fast and low- power SRAMs in industry-standard package options. The device also features embedded ECC. logic which can detect and correct single-bit errors in the accessed location. Product Portfolio Power Dissipation Operating I , CC Speed Standby, I Deep-Sleep 2 (mA) SB2 Product Range V Range (V) CC (ns) (mA) current (A) f = f max 3 3 3 Typ Max Typ Max Typ Max CY7S1041G(E)18 1.65 V2.2 V 15 40 6 8 15 CY7S1041G(E)30 Industrial 2.2 V3.6 V 10 38 45 CY7S1041G(E) 4.55.5 V 10 38 45 Notes 1. This device does not support automatic write back on error detection. 2. ERR pin is available only for devices which have ERR option E in the ordering code. Refer Ordering Information for details. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for V range of 1.65 V 2.2 V), CC CC V =3V (for V range of 2.2 V 3.6 V), and V = 5 V (for V range of 4.5 V 5.5 V), T = 25 C. CC CC CC CC A Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-92576 Rev. *G Revised January 5, 2018CY7S1041G CY7S1041GE Logic Block Diagram CY7S1041G / CY7S1041GE ECCENCODER INPUTBUFFER A0 A1 ERR(Optional) A2 A3 I/O I/O MEMORY 0 7 A4 ARRAY A5 I/O I/O 8 15 A6 A7 A8 A9 COLUMNDECODER BHE WE POWERMANAGEMENT CE DS OE BLOCK BLE Document Number: 001-92576 Rev. *G Page 2 of 22 ROWDECODER A10 A11 A12 A13 A14 A15 A16 A17 SENSEAMPLIFIERS ECCDECODER