CY7S1049G CY7S1049GE 4-Mbit (512K words 8-bit) Static RAM with PowerSnooze and Error Correcting Code (ECC) 4-Mbit (512K words 8-bit) Static RAM with PowerSnooze and Error Correcting Code (ECC) 3 ultra-low power Deep-Sleep mode . With Deep-Sleep mode Features currents as low as 15 A, the CY7S1049G/CY7S1049GE High speed devices combine the best features of fast and low- power SRAMs Access time (t ) = 10 ns / 15 ns AA in industry-standard package options. The device also features embedded ECC. logic which can detect and correct single-bit Ultra-low power Deep-Sleep (DS) current errors in the accessed location. I = 15 A DS Deep-Sleep input (DS) must be deasserted HIGH for normal Low active and standby currents operating mode. Active Current I = 38-mA typical CC To perform data writes, assert the Chip Enable (CE) and Write Standby Current I = 6-mA typical SB2 Enable (WE) inputs LOW, and provide the data and address on Wide operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, device data pins (I/O through I/O ) and address pins (A 0 7 0 4.5 V to 5.5 V through A ) respectively. 18 1, 2 Embedded ECC for single-bit error correction To perform data reads, assert the Chip Enable (CE) and Output Error indication (ERR) pin to indicate 1-bit error detection and Enable (OE) inputs LOW and provide the required address on correction the address lines. Read data is accessible on the I/O lines (I/O 0 through I/O ). 7 1.0-V data retention The device is placed in a low-power Deep-Sleep mode when the TTL- compatible inputs and outputs Deep-Sleep input (DS) is asserted LOW. In this state, the device Available in Pb-free 44-pin TSOP II, and 36-pin (400-mil) is disabled for normal operation and is placed in a low power data molded SOJ retention mode. The device can be activated by deasserting the Deep-Sleep input (DS) to HIGH. Functional Description The CY7S1049G is available in 44-pin TSOP II, and 36-pin 1 The CY7S1049G/CY7S1049GE is a high-performance Molded SOJ (400 Mils). PowerSnooze static RAM organized as 512K words 8 bits. This device features fast access times (10 ns) and a unique Product Portfolio Power Dissipation Operating I , CC Speed Standby, I Deep-Sleep 4 (mA) SB2 Product Range V Range (V) CC (ns) (mA) current (A) f = f max 5 5 5 Typ Max Typ Max Typ Max CY7S1049G(E)18 Industrial 1.65 V2.2 V 15 40 6 8 15 CY7S1049G(E)30 2.2 V3.6 V 10 38 45 CY7S1049G(E) 4.55.5 V 10 38 45 Notes 1. This device does not support automatic write back on error detection. 2. SER FIT Rate <0.1 FIT/Mb. Refer AN88889 for details. 3. Refer AN89371 for details on PowerSnooze feature. 4. ERR pin is available only for devices which have ERR option E in the ordering code. Refer Ordering Information on page 17 for details. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = 1.8 V (for V range of 1.65 V2.2 V), V =3V CC CC CC (for V range of 2.2 V3.6 V), and V = 5 V (for V range of 4.5 V5.5 V), T = 25 C. CC CC CC A Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-95414 Rev. *F Revised April 3, 2018CY7S1049G CY7S1049GE Logic Block Diagram CY7S1049G DATA IN ECCENCODER DRIVERS A0 A1 A2 A3 I/O I/O 512Kx8 0 7 A4 RAMARRAY A5 A6 A7 A8 A9 COLUMN DECODER WE CE OE Power Management DS Block Logic Block Diagram CY7S1049GE DATA IN ECCENCODER DRIVERS A0 A1 A2 A3 512Kx8 I/O I/O 0 7 A4 RAMARRAY A5 ERR A6 A7 A8 A9 COLUMN WE CE DECODER OE Power Management DS Block Document Number: 001-95414 Rev. *F Page 2 of 21 ROWDECODER ROWDECODER A10 A11 A12 A10 A13 A11 A14 A12 A15 A13 A16 A14 A17 A15 A18 A16 A17 A18 SENSE SENSE AMPLIFIERS AMPLIFIERS ECCDECODER ECCDECODER