Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as Cypress document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.comCY7S1061G/CY7S1061GE 16-Mbit (1 M words 16 bit) Static RAM with PowerSnooze and ECC 16-Mbit (1 M words 16 bit) Static RAM with PowerSnooze and Error Correcting Code (ECC) To access devices with a single-chip enable input, assert the chip Features enable input (CE) LOW. To access dual chip enable devices, High speed assert both chip enable inputs CE as LOW and CE as HIGH. 1 2 t = 10 ns AA To perform data writes, assert the Write Enable (WE) input LOW, 1 and provide the data and address on device data pins (I/O Ultra-low power PowerSnooze device 0 through I/O ) and address pins (A through A ) respectively. 15 0 19 Deep Sleep (DS) current I = 22-A maximum DS The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs Low active and standby currents control byte writes, and write data on the corresponding I/O lines to the memory location specified. BHE controls I/O through I = 90-mA typical 8 CC I/O and BLE controls I/O through I/O . I = 20-mA typical 15 0 7 SB2 To perform data reads, assert the Output Enable (OE) input and Wide operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, provide the required address on the address lines. Read data is and 4.5 V to 5.5 V accessible on the I/O lines (I/O through I/O ). You can perform 0 15 Embedded error-correcting code (ECC) for single-bit error byte accesses by asserting the required byte enable signal (BHE correction or BLE) to read either the upper byte or the lower byte of data from the specified address location. 1.0-V data retention All I/Os (I/O through I/O ) are placed in a high-impedance state 0 15 Transistor-transistor logic (TTL) compatible inputs and outputs when the device is deselected (CE HIGH for single chip enable devices and CE HIGH and CE LOW for dual chip enable Error indication (ERR) pin to indicate 1-bit error detection and 1 2 correction devices), or the control signals (OE, BLE, BHE) are de-asserted. The device is placed in a low power Deep Sleep mode when the Available in Pb-free 48-pin TSOP I, 54-pin TSOP II, and 48-ball VFBGA packages Deep Sleep pin (DS) is LOW. In this state, the device is disabled for normal operation and is placed in a data retention mode. The Functional Description device can be activated by de-asserting the Deep Sleep pin (DS HIGH). The CY7S1061G/CY7S1061GE is a high-performance CMOS fast static RAM organized as 1,048,576 words by 16 bits. This The CY7S1061G/CY7S1061G is available in 48-pin TSOP I, device features fast access times (10 ns) and a unique ultra-low 54-pin TSOP II, and 48-ball VFBGA packages. power Deep Sleep mode. With Sleep mode currents as low as For a complete list of related resources, click here. 22 A, the CY7S1061G device combines the best features of fast and low-power SRAM in industry-standard package options. 2 The device also features embedded ECC . ECC logic can detect and correct single-bit error in the accessed location. The CY7S1061GE device includes an ERR pin that signals an error-detection and correction event during a read cycle. Product Portfolio Current Consumption Operating I CC Speed (mA) Product Range V Range (V) Standby, I (mA) Deep-Sleep Current (A) CC SB2 (ns) f = f max 3 3 1 Typ Max Typ Max Typ Max CY7S1061G18 1.65 V2.2 V 15 70 80 CY7S1061G(E)30 Industrial 2.2 V3.6 V 10 90 110 20 30 8 22 CY7S1061G 4.55.5 V 10 90 110 Notes 1. Refer to AN89371 for details on PowerSnooze feature of this device. 2. This device does not support automatic write-back on error detection. = 1.8 V (for a V range of 1.65 V2.2 V), 3. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V CC CC V = 3 V (for a V range of 2.2 V3.6 V), and V = 5 V (for a V range of 4.5 V5.5 V), T = 25 C. CC CC CC CC A Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-79707 Rev. *N Revised September 15, 2016