CYDC128B16-55AXI Infineon

CYDC128B16 1.8 V 4 K/8 K/16 K 16 and 8 K/16 K 8 ConsuMoBL Dual-Port Static RAM Features True dual-ported memory cells which allow simultaneous Full asynchronous operation access of the same memory location Pin select for master or slave 4/8/16 K 16 and 8/16 K 8 organization Expandable data bus to 32 bits with master/slave chip select High speed access: 40 ns when using more than one device Ultra low operating power On-chip arbitration logic Active: I = 15 mA (typical) at 55 ns CC On-chip semaphore logic Active: I = 25 mA (typical) at 40 ns CC Input read registers (IRR) and output drive registers (ODR) Standby: I = 2 A (typical) SB3 INT flag for port-to-port communication Port-independent 1.8 V, 2.5 V, and 3.0 V I/Os Separate upper byte and lower byte control Pb-free 14 14 1.4 mm 100-pin Thin Quad Flat Pack (TQFP) Package Commercial and industrial temperature ranges Selection Guide for V = 1.8 V CC CYDC128B16 CYDC128B16 Description 40 55 Unit Port I/O Voltages (P1-P2) 1.8 V-1.8 V 1.8 V-1.8 V Maximum Access Time 40 55 ns Typical Operating Current 25 15 mA Typical Standby Current for I 22 A SB1 Typical Standby Current for I 22 A SB3 Selection Guide for V = 2.5 V CC CYDC128B16 CYDC128B16 Description 40 55 Unit Port I/O Voltages (P1-P2) 2.5 V-2.5 V 2.5 V-2.5 V Maximum Access Time 40 55 ns Typical Operating Current 39 28 mA Typical Standby Current for I 66 A SB1 Typical Standby Current for I 44 A SB3 Selection Guide for V = 3.0 V CC CYDC128B16 CYDC128B16 Description 40 55 Unit Port I/O Voltages (P1-P2) 3.0 V-3.0 V 3.0 V-3.0 V Maximum Access Time 40 55 ns Typical Operating Current 49 42 mA Typical Standby Current for I 77 A SB1 Typical Standby Current for I 66 A SB3 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 001-01638 Rev. *I Revised March 7, 2014 CYDC128B16 1, 2 Top Level Block Diagram I/O 15:0 R I/O 15:0 L UB R UB L LB LB L R IO IO Control Control 16K X 16 Dual Ported Array Address Decode Address Decode A 13:0 L A 13:0 R CE L CE R Interrupt OE L OE R Arbitration R/W R/W R L Semaphore SEM R SEM L BUSY R BUSY L M/S INT Mailboxes L INT R Input Read Register and CE CE L R Output Drive OE OE L R Register R/W R/W L R IRR ,IRR 0 1 ODR - ODR 0 4 SFEN Notes 1. A A for 4k devices A A for 8k devices A A for 16k devices. 0 11 0 12 0 13 2. BUSY is an output in master mode and an input in slave mode. Document Number: 001-01638 Rev. *I Page 2 of 31